Theoretical Analyses of Complete 3-D Reduced Surface Field LDMOS With Folded-Substrate Breaking Limit of Superjunction LDMOS

Cao, Zhen; Duan, Baoxing; Cai, Hai; Yuan, Shuai; Yang, Yong

doi:10.1109/ted.2016.2615654

Cited by 19 publications

(5 citation statements)

References 27 publications

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“…However, there is a contradictory relationship between the BV and R on,sp of VDMOS, and R on,sp increases sharply with the increase in BV . In order to alleviate this contradictory relationship, several new structures were proposed [ 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 ]. With the advances in the technology, the functions of Si-based power devices are gradually approaching the limits of Si materials.…”

Section: Introductionmentioning

confidence: 99%

GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance

2023

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A novel VDMOS with the GaN/Si heterojunction (GaN/Si VDMOS) is proposed in this letter to optimize the breakdown voltage (BV) and the specific on-resistance (Ron,sp) by Breakdown Point Transfer (BPT), which transfers the breakdown point from the high-electric-field region to the low-electric-field region and improves the BV compared with conventional Si VDMOS. The results of the TCAD simulation show that the optimized BV of the proposed GaN/Si VDMOS increases from 374 V to 2029 V compared with the conventional Si VDMOS with the same drift region length of 20 μm, and the Ron,sp of 17.2 mΩ·cm2 is lower than 36.5 mΩ·cm2 for the conventional Si VDMOS. Due to the introduction of the GaN/Si heterojunction, the breakdown point is transferred by BPT from the higher-electric-field region with the largest radius of curvature to the low-electric-field region. The interfacial state effects of the GaN/Si are analyzed to guide the fabrication of the GaN/Si heterojunction MOSFETs.

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Section: Introductionmentioning

confidence: 99%

GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance

2023

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“…A vertical double-diffusion metal oxide semiconductor (VDMOS) is an important component in the field of power semiconductor devices; due to its fast switching speed, low loss, high input impedance, low driving power, and excellent frequency characteristics, it has been widely used in power integrated circuits and power integrated systems [1][2][3][4][5][6][7][8][9][10]. However, the main problem of VDMOS power devices is that the specific on-resistance (R on,sp ) of the device increases sharply with an increase in breakdown voltage (BV), which greatly limits the development and application of VDMOS power devices [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

Analysis of SiC/Si Heterojunction Band Energy and Interface State Characteristics for SiC/Si VDMOS

Yang,

Duan,

Yang

2023

Micromachines

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SiC/Si and GaN/Si heterojunction technology has been widely used in power semiconductor devices, and SiC/Si VDMOS and GaN/Si VDMOS were proposed in our previous paper. Based on existing research, breakdown point transfer technology (BPT) was used to optimize SiC/Si VDMOS. Simulation results showed that the BV of the SiC/Si heterojunction VDMOS was considerably increased from 259 V to 1144 V, and Ron,sp decreased from 18.2 mΩ·cm2 to 6.03 mΩ·cm2 compared with Si VDMOS. In order to analyze the characteristics of the SiC/Si heterojunction structure deeply, the influence of the interface state characteristics of the SiC/Si heterojunction on the electrical parameters of VDMOS was analyzed, including electric field characteristics, blocking characteristics, output characteristics, and transfer characteristics. In addition, the influence of the interface state of the SiC/Si heterojunction on energy band characteristics was analyzed. The results showed that with an increase in the interfacial charge (acceptor) concentration, the p-type trap layer was introduced into the interface of the SiC/Si heterojunction, energy increased slightly, and the barrier height difference at the heterojunction increased, resulting in an increase in BV. At the same time, since the barrier height became higher, electrons did not flow easily, so Ron,sp increased. On the contrary, when a charge (donor) was introduced at the interface of the SiC/Si heterojunction, the number of electrons in the channel increased, resulting in an increase in the electron current, which is conducive to the flow of electrons, resulting in a decrease in Ron,sp. The energy band and other characteristics of devices with temperature were simulated at different temperatures. Finally, the effects of SiC/Si heterojunction interface states on interface capacitances and switching performances of VDMOS devices were also discussed.

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“…Based on the common structure of T-LDMOS, many improved structures are proposed [4]- [12], such as the ones with vertical field plates in the trench [7]- [9], and the ones with variable-k trench-dielectric [10]- [12]. Recently, many studies start applying a well-known technique of super junction (SJ) to the LDMOS [13]- [16], as well as to the T-LDMOS [17]- [20], such as the T-LDMOS with a quasi vertical (QV) SJ structure [17], [19], [20] and that with a lateral SJ structure at the trench bottom [18]. However, because the trench acts as a capacitor in the off-state and disturbs the surface electric-field (e-field) distribution [19], a QVSJ structure in T-LDMOS is hard to satisfy the important charge-balanced condition and, therefore, cannot be fully used to improve the device performance.…”

Section: Introductionmentioning

confidence: 99%

“…It features a resistive field plate (RFP) which is embedded in the trench and surrounded by the QVSJ drift region. Since RFP can modulate the surface e-field distribution [16], [21]- [24] and eliminate the impact of the trench capacitor, the QVSJ region in this device is able to satisfy the charge-balanced condition. Moreover, because the realization of RFP does not need any additional mask, the fabrication process is barely complicated.…”

Section: Introductionmentioning

confidence: 99%

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cheng

Chen

et al. 2019

IEEE J. Electron Devices Soc.

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An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance. The realization of RFP barely complicates the device fabrication, but it motivates QVSJ to significantly improve the relationship between breakdown voltage (BV) and specific on-state resistance (R ON,SP). The simulation results show that compared with the conventional QVSJ T-LDMOS, the proposed one gains the R ON,SP reduced by about 79% under the same BV requirement of about 500 V. It therefore presents an excellent figure of merit (FOM) (FOM = BV 2 /R ON,SP , Baliga's FOM) up to 29.8 MW/cm 2 , which is superior to the prior art and exhibits a bright prospect of saving energy. INDEX TERMS Trench LDMOS (T-LDMOS), quasi vertical super junction (QVSJ), resistive field plate (RFP).

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Theoretical Analyses of Complete 3-D Reduced Surface Field LDMOS With Folded-Substrate Breaking Limit of Superjunction LDMOS

Cited by 19 publications

References 27 publications

GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance

GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance

Analysis of SiC/Si Heterojunction Band Energy and Interface State Characteristics for SiC/Si VDMOS

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

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