A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cheng, Junji; Wu, Shuangyi; Chen, Weizhen; Huang, Haimeng; Yi, Bo

doi:10.1109/jeds.2019.2928091

Cited by 6 publications

(2 citation statements)

References 36 publications

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“…The mass production of consumer electronic devices has recently increased the demand for power integrated circuits [1], [2], [3]. Silicon-based laterally-diffused metaloxide-semiconductor (LDMOS) field-effect transistors are widely used in low-voltage to high-voltage power electronic applications [4], [5], [6], [7], [8], [9]. LDMOS can easily be integrated with bipolar junction transistors and CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Chuang,

Saadat,

Van De Put

et al. 2023

IEEE Access

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We propose a pioneering approach that integrates optimization algorithms and technology computer-aided design to automatically optimize laterally-diffused metal-oxide-semiconductors (LDMOS) with a field-oxide structure. We define the ratio of the square of the breakdown voltage divided by the specific on-resistance as the figure-of-merit (FOM) and the objective function of our optimization. We compare the performance of three different algorithms: Nelder-Mead, Powell, and Bayesian Optimization. We show how the LDMOS performance evolves as each of the three optimization algorithms reach their optimized structure. We show that a straightforward Nelder-Mead optimization leads to a local optimum when optimizing over six input parameters. We find that Bayesian Optimization is the most data-efficient method to find the global optimized structure in the multi-domain design space.INDEX TERMS Bayesian optimization, LDMOS, nelder-mead algorithm, power semiconductor device, powell algorithm, step gate field oxide structure.

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Section: Introductionmentioning

confidence: 99%

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Chuang,

Saadat,

Van De Put

et al. 2023

IEEE Access

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show abstract

“…Some authors use additional N-type impurities to compensate for the SAD [6] [8]. Then some reported structures based on the N-buffer SJ-LDMOS are all focusing on the optimization of the lateral and bulk electric field distributions of the device to further improve the BV, using the technology of resistive field plates [9][10], stepped doping buffer layers [11][12], N-type buried layers [13][14], deep drain diffusion [15], high-K dielectric trench [16], etc. However, the RON,sp of the N-buffer SJ-LDMOS structures is still limited at high voltage ratings (~600V).…”

Section: Introductionmentioning

confidence: 99%

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Cao

Jiao

2020

IEEE J. Electron Devices Soc.

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In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (RON,sp) of 28.53 mΩ• cm 2 , which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV 2 /RON,sp of DG SJ-LDMOS is increased by 85.5 %.

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A super-junction SOI-LDMOS with low resistance electron channel

Chen¹,

Huang²,

Huang³

et al. 2021

Chinese Phys. B

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A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (R on,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm2, respectively, and the Baliga’s figure of merit (FOM = BV 2/R on,sp) of 4.1 MW/cm2 is achieved, breaking through the silicon limit.

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A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cited by 6 publications

References 36 publications

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

A super-junction SOI-LDMOS with low resistance electron channel

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