Theoretical and experimental behavior of monolithically integrated crystalline silicon solar cells

Abstract

A concept for the fabrication of monolithically integrated silicon solar cells is presented. The concept is based on standard Si wafer technology and does not use thin-film approaches. A key feature is isolation trenches dividing the wafer into several unit solar cells. Due to the imperfect isolation between unit cells defined on the same conductive wafer, some device aspects deviating from an ordinary series connection of solar cells arise. For the theoretical description, a model proposed by Valco et al. [G. J. Valco, V. J. Kapoor, J. C. Evans, Jr., and A. T. Chin, in Proceedings of the 15th IEEE Photovoltaic Specialists Conference, Orlando, FL (1981), p. 187] has been generalized by using a two-diode concept for the unit cells and by weakening the assumption of identical unit cells. The model was used to simulate the cell performance in dependence on light intensity, isolation resistance, cell area, and number of unit cells. As a result, general design rules for these truly monolithically integrated solar cells are given. The theoretical predictions could be partially confirmed by experimental prototypes. The best cell with a total area of 21 cm2 and six unit cells exhibits an open-circuit voltage of 3.43 V and a conversion efficiency of 10.9% under 100 mW/cm2 AM1.5G illumination and standard reporting conditions.

Fabrication of monolithic photovoltaic arrays on crystalline silicon by wafer bonding and deep etching techniques

“…8,13 The results obtained so far are in general promising, but many problems remain as the efficiencies reported are much lower than state of the art technology for individual cells. This is due to a number of reasons: poor isolation between contiguous solar cells, 11 lifetime degradation during array processing, 20,21 poor surface passivation, high series resistance due to interconnects and faulty devices due to unwanted shunts or open circuits. Most of the monolithic solutions based on c-Si shown in the literature 11 have areas in the range of 10 cm 2 , while designs based on a-Si 6,18 show areas of 1 mm 2 or 1 cm 2 .…”

“…4 Since the early 1980s efforts have been reported to design and fabricate small and medium-size photovoltaic arrays by a number of technologies: multichip module (MCM); 1,5 thin-film, either amorphous, 6 polycrystalline, 7 or epitaxial 8 silicon; gallium arsenide, 9,10 or crystalline silicon monolithic. 11,12 c-Si monolithic technology has clear advantages arising from the mature and advanced mainstream silicon batch processing technology and its potential compatibility with other devices such as sensor or actuators, besides processing electronics. 13 The area of application of PV arrays in MEMS (micro-electro-mechanical systems) was identified some years ago 6 and recently it has been shown 14 that a photovoltaic drive can be a suitable way to raise a low d.c. voltage to a higher value in order to drive MEMS devices based on pull-in, 15 avoiding some of the drawbacks of conventional drives.…”

“…19 In other approaches a c-Si wafer is used as a handling wafer and the devices are placed in the same c-Si wafer. 11 Unit cells are not totally isolated through the bulk, which simplifies the fabrication process, but decreases the photovoltaic response of the device. Other c-Si monolithic approaches consist on unit cells isolated by a RIE (reactive ion etching) steps.…”

“…Moreover, handling or substrate material has been reported for glass 16,17 and semiinsulated semiconductors, 9 or silicon dioxide in SOI wafers. 11,13 Most monolithic photovoltaic modules use an insulating substrate in which silicon is deposited. 6,18 A polysilicon film is grown on a ceramic substrate and the unit cells are isolated with a saw or with anisotropic etching of silicon.…”

“…Several approaches have been followed to isolate individual cells from one another: trench isolation with anisotropic etching of silicon, 16 V-groove, 17 wafer through-holes, 11 to interconnect them in series: wire bonding, 11 metal photolithography, 16 etc. Moreover, handling or substrate material has been reported for glass 16,17 and semiinsulated semiconductors, 9 or silicon dioxide in SOI wafers.…”