Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

Roy, Sujoy Sinha; Rebeiro, Chester; Mukhopadhyay, Debdeep

doi:10.1109/tvlsi.2012.2198502

Cited by 47 publications

(51 citation statements)

References 15 publications

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“…Thus, pipelining is often adopted to shorten the critical path delay. Moreover, some multiplication algorithms (such as Karatsuba) are used to improve area and time complexity [10,11,23]. For the high-speed end of the design space, large digit serial multipliers or bit parallel multipliers (such as school book and Mastrovito) are often used.…”

Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

“…Thus, the main optimization of the large multiplier is concentrated on the GF2MUL part. There are several high performance bit parallel multipliers in the literature [11], [19], [20], [26], and [27]. The complexity of a bit parallel multiplier can be quadratic or subquadratic [18].…”

Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

“…Subquadratic multipliers are mostly based on the Karatsuba algorithm to reduce the area complexity at the expense of a lower clock frequency. The performance of the Karatsuba based bit parallel multiplier is improved by adopting pipelining techniques [11]. In the next section, we present a novel high performance full-precision GF(2 m ) multiplier with segmented pipelining.…”

Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

“…The six multiplications can, for example, be computed in two steps using three multipliers or in three steps using two multipliers or in six steps by serial multiplications using one multiplier [17], [13] and [10]. Again, the digit size can affect the performance of ECC; for example, a bit serial implementation takes m cycles, a digit ( bits) serial one takes ( / ) cycles and a bit parallel implementation takes a single clock cycle [8], [12] and [11]. In the case of high speed design, digit serial multipliers are considered to reduce latency.…”

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

“…Many high performance ECC processor implementations on FPGA have been reported in the literature; the most relevant are presented in [10], [11], [12], [13], [14], [15], [16], [17], [20], [21], [22], and [23]. The common optimizing technique of high speed designs is the reduction of latency (number of clock Z. U.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a novel high speed ECC processor implementation for point multiplication on Field Programmable Gate Array (FPGA) is proposed. A new segmented pipelined fullprecision multiplier is used to reduce the latency and the LopezDahab (LD) Montgomery point multiplication algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles required. The proposed ECC architecture has been implemented on Xilinx FPGAs Virtex4, Virtex5 and Virtex7 families. To our knowledge, our single multiplier and three multipliers based designs show the fastest performance to date when compared to reported works individually. Our one multiplier based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the more advanced Virtex7, (3.18 µs at 352 MHz). Finally, the proposed three multiplier based ECC implementation is the first work reporting the lowest number of clock cycles and the fastest ECC processor design on FPGA (450 clock cycles to get 2.83 µs on Virtex7).

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Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

Section: Full-precision Multiplier For Ecc Applicationmentioning

confidence: 99%

Section: A Point Multiplication Without Pipelining Delaymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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Efficient hardware implementations of point multiplication for binary Edwards curves

Rashidi

2018

Circuit Theory & Apps

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SummaryThis paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.

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A Reconfigurable Implementation of Elliptic Curve Cryptography over GF ($$2^{n}$$)

Harb

Ahmad

Swamy

2020

E-Business and Telecommunications

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Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

Cited by 47 publications

References 15 publications

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Efficient hardware implementations of point multiplication for binary Edwards curves

A Reconfigurable Implementation of Elliptic Curve Cryptography over GF ($$2^{n}$$)

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