Theory and design of advanced CMOS current mirrors

Tzschoppe, Christoph; Jorges, Udo; Richter, A.; Lindner, Bastian; Ellinger, Frank

doi:10.1109/imoc.2015.7369125

Cited by 17 publications

(5 citation statements)

References 7 publications

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“…The preprocessor works in the current mode; therefore, the addition operations are carried out in the nodes in accordance with the first Kirchhoff's law and do not require the use of any additional circuits. The preprocessor additionally uses other modules, e.g., single-and multi-output current mirrors (CMs) [25], the size and number of which depend on the structure of the classifier. The implementation details of the modules and the preprocessor itself are described in paper [5].…”

Section: Weak Inversion Modementioning

confidence: 99%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

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Section: Weak Inversion Modementioning

confidence: 99%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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“…The swing of the DCO output signal varied, so this block was intended to optimize swing within the normal range. This block could adjust LC DCO power consumption to the optimum and had a current mirror as the base element [7]. The sizes of the current control transistors M3 and M4 were chosen in such a way that the output current was double that of the control current.…”

Section: Current Control Blockmentioning

confidence: 99%

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Mačaitis

Navickas

2019

Electronics

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This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

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“…Esant skirtingoms aplinkos sąlygoms LC-SVG išėjimo signalo amplitudė gali skirtis, srovės valdymo blokas naudojamas palaikyti LC-SVG išėjimo signalo amplitudę optimaliuose rėžiuose. Taip pat šis blokas naudojamas energijos suvartojimo optimizavimui (Tzschoppe, Jorges, Richter, Lindner, & Ellinger, 2015). Srovės valdymo bloko realizavimui panaudotas srovės veidrodis.…”

Section: Srovės Valdymo Blokasunclassified

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

Mačaitis¹

2019

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Disertacija rengta 2015-2019 metais Valstybiniame mokslinių tyrimų institute Fizinių ir technologijos mokslų centre. Vadovas prof. habil. dr. Romualdas NAVICKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Vilniaus Gedimino technikos universiteto elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo taryba: Pirmininkas prof. dr. Šarūnas PAULIKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Nariai: dr. Alvydas LISAUSKAS (Lenkijos mokslų akademijos Aukšto slėgio fizikos institutas, fizika -N 002), dr. Vitalij NOVICKIJ (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001), dr. Česlovas ŠIMKEVIČIUS (Valstybinis mokslinių tyrimų institutas Fizinių ir technologijos mokslų centras, elektros ir elektronikos inžinerija -T 001), prof. dr. Algimantas VALINEVIČIUS (Kauno technologijos universitetas, elektros ir elektronikos inžinerija -T 001). Disertacija bus ginama viešame Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo tarybos posėdyje 2019 m. lapkričio 8 d. 13 val. Valstybinio mokslinių tyrimų instituto Fizinių ir technologijos mokslų centro posėdžių salėje D401.

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Theory and design of advanced CMOS current mirrors

Cited by 17 publications

References 7 publications

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

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