Theory of the Junctionless Nanowire FET

Gnani, Elena; Gnudi, A.; Reggiani, Susanna; Baccarani, G.

doi:10.1109/ted.2011.2159608

Cited by 219 publications

(88 citation statements)

References 18 publications

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“…The junction less transistor (JLT) is one of the most promising candidates for sub-22 nm technology node. Theory of JLT is reported in [1][2][3][4][5][6]. The JLT is a transistor without junction [1].…”

Section: Introductionmentioning

confidence: 99%

“…It has an identical doping profile throughout the source, drain and channel [1]. Due to the absence of junctions, JLT has several features like simpler fabrication without deep source, drain implants, extremely low short channel effects, extremely low leakage current with nearly ideal subthreshold slope and optimal control of gate over the channel potential [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

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An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

Sarma

Sharma

2015

J Comput Electron

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A novel 2-D analytical potential model of source and drain region along with channel for a fully depleted symmetric double gate junction less transistor is presented in this paper. The boundary conditions for channel potential along the channel length is taken considering source and drain region and boundary conditions for source and drain potential model are derived from channel longitudinal potential expression. The potential model is validated using TCAD simulations. A method for scale length determination is also presented. Scale length expression is obtained from the transverse electrostatic potential expression. Scale length variation with silicon layer thickness and gate oxide thickness is shown. The dependence of Scale length on the dielectric constant is also shown for the three dielectrics-"SiO 2 ", "Al 2 O 3 " and "HfO 2 ".

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

Sarma

Sharma

2015

J Comput Electron

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“…The transconductance in junctionless (JL) transistor is however lesser compared to JB transistor. Device variability and the parasitic source/drain resistances are acknowledged as important limitations of the JL nanowire field-effect transistors [2].…”

Section: Introductionmentioning

confidence: 99%

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Baruah

Paily

2015

J Comput Electron

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Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

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“…The junction-less FET has a bulk-current conduction mechanism [7], we know that under the condition of channel being fully depleted the transistor is in off condition. We know that the operation of a MOS device is a function of gate voltage hence initially when the gate voltage is less than the threshold voltage the device is in sub-threshold state and the channel is fully depleted [8][9][10][11][12][13][14]. Now with increase in gate voltage greater than the threshold voltage of the device the channel now becomes partially depleted and the current flows by bulk-current conduction mechanism through the center of the channel.…”

Section: Introductionmentioning

confidence: 99%

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

Roy

Gupta

Rai

2015

Microelectronics Journal

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Theory of the Junctionless Nanowire FET

Cited by 219 publications

References 18 publications

An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

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