This work described the fabrication and performances of strained channel In 0.52 Al 0.47 As/In 0.7 Ga 0.3 As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 • C for 35 min, a 10 nm Pd-gate device displays a V TH of −0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing V TH = −0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm −1 (from 500 mS mm −1 ), a high I DSmax of 400 mA mm −1 (from 330 mA mm −1 ) and good f T and f max of 24.5 and 49 GHz commensurate with the 1 μm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 • C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.