2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems 2012
DOI: 10.1109/epeps.2012.6457910
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Thermal characterization of TSV based 3D stacked ICs

Abstract: This paper studies the thermal impact and characterization of Through Silicon Vias (TSVs) in stacked three dimensional (3D) integrated circuits (ICs) through finiteelement based numerical analysis. Realistic 3D stacked ICs are built using a commercial finite-element based modeling and analysis tool, COMSOL. Thermal profiles along with thermal impact of TSVs are studied for two layer and three layer stacked IC structures under practical power inputs. Experimental results show that there is a significant tempera… Show more

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Cited by 12 publications
(3 citation statements)
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“…The thermal conductivities of the silicon dioxide and the silicon substrate are denoted by 2 SiO k and Si k , respectively.…”
Section: Thermal Model For Metal Core In a Single Tsvmentioning
confidence: 99%
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“…The thermal conductivities of the silicon dioxide and the silicon substrate are denoted by 2 SiO k and Si k , respectively.…”
Section: Thermal Model For Metal Core In a Single Tsvmentioning
confidence: 99%
“…3(c), where 1 R is the thermal resistance of self-heating and 2 R is that of thermal coupling effects. They can be calculated as 2 1…”
Section: A Model Of Signal-ground (Sg) Tsv Structurementioning
confidence: 99%
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