Thermal Conductivity Model to Analyze the Thermal Implications in Nanowire FETs

Kumar, Nitish; Kaushik, Pragyey Kumar; Kumar, Sushil; Gupta, Ankur; Singh, Pushpapraj

doi:10.1109/ted.2022.3208848

Cited by 12 publications

(3 citation statements)

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“…where µ n0 is the without strain mobility, m nl and m nt are the electron longitudinal and transverse masses in the sub-valley, respectively, and F n is the quasi-Fermi level of electrons. Some additional models are also used in simulation, such as hydrodynamic, bandgap narrowing, density gradient, mobility degradation (scattering and high field effects), band-to-band tunneling, and SRH recombination, which are discussed in detail in [9,[23][24][25]. The model calibration results with experimental data of JL-NW GAA FET [12] are verified, as shown in figure 3, which shows well agreement between simulation and experimental data.…”

Section: Computational Physical Modelmentioning

confidence: 69%

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Kumar,

Joshi,

Gupta

et al. 2024

Nanotechnology

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In this paper, the piezoresistive sensitivity is enhanced by applying uniform mechanical stress (MS) on the multi-nanosheet (NS) channels of sub-5 nm junctionless field-effect transistors (FETs). The piezoresistivity of the sensing device is boosted by narrowing channel conductivity using low gate biasing and reducing physical channel width, resulting in the maximum (~6 times higher) sensitivity observed in the subthreshold regime compared to the ON-state condition. In addition, the sensitivity is extensively increased by ~30.3% near the threshold voltage (VTH) with horizontally multi-NS stacking due to the uniform MS distribution on the multi-NS channels, which can sense slight deflection of pressure on the circular diaphragm. These results show that the tunable sensitivity of junctionless multi-channel devices is superior to the inversion mode, a consequence of the less scattering effect, better thermal stability, and low electronic noise.

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Section: Computational Physical Modelmentioning

confidence: 69%

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Kumar,

Joshi,

Gupta

et al. 2024

Nanotechnology

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“…The high T amb can change the temperature-sensitivity threshold voltage (V th ) and introduce variability in the on-state current. At the same time, the T amb plays a crucial role in thermal properties, such as thermal conductivity, lattice temperature rise, and thermal resistance (R th ) [20][21][22][23][24][25]. Some researchers have analyzed the electrothermal characteristics of FinFETs with multiple fins under the impact of T amb [20,23,26].…”

Section: Introductionmentioning

confidence: 99%

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

Zhao,

Cao,

Wang

et al. 2023

Nanomaterials

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With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

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“…Tsen et al [23] proposed inter-bridges between stacked channels to improve the device heat dissipation and reduce temperature difference among the channels of treeFET. Kumar et al [24] investigated the influence of doping concentration and ambient temperature on the self-heating of the device in SNSHFET. Jeong et al [25] proposed a trench inner spacer to reduce the thermal resistance and thereby the lattice temperature of nanosheet FET.…”

mentioning

confidence: 99%

Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs

Balasubbareddy,

Sivasankaran

2024

IEEE Access

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The stacked nanosheet field effect transistor (SNSHFET) exhibits superior electrostatic performance with its increased effective channel width. However, as the technology node progressing towards angstrom dimensions, self-heating became one of the major challenges in SNSHFETs due to their confined geometry. The self-heating impacts not only the respective device, but also its contiguous device on the same substrate. In this paper, the thermal impact of heat stacked nanosheet FET (He-FET) on proximal cool stacked nanosheet FET (Co-FET) is studied at 7 nm technology node. Thermal impact on DC and analog/RF performance of Co-FET is deliberated by varying the inter-device spacing (IDS) and shallow trench isolation (STI) depth between the two stacked nanosheet FETs. It has been observed that, self-heating induced thermal energy of He-FET shows more impact on the bottom channels compared to the top channels in the Co-FET. The electron mobility is reduced by 4.25% in the channel near to the substrate compared to the channel near to contacts. The transit frequency (f T ) and the maximum oscillation frequency (f max ) of 131.5 GHz and 435 GHz were obtained, respectively with the optimization of IDS of 30 nm and STI depth of 50 nm. INDEX TERMSInter-device spacing, Self-heating, Shallow trench isolation depth, Stacked nanosheet FET, Thermal intrude.

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Thermal Conductivity Model to Analyze the Thermal Implications in Nanowire FETs

Cited by 12 publications

References 0 publications

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs

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