Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system

Haberfehlner, Georg; Bychikhin, S.; Dubec, V.; Heer, Michael; Podgaynaya, Alja; Pfost, Martin; Stecher, M.; Gornik, E.; Pogány, D.

doi:10.1016/j.microrel.2009.07.032

Cited by 12 publications

(4 citation statements)

References 16 publications

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“…2D holographic interferometry technique (10 ls time resolution [9,12]) and scanning heterodyne interferometer (3 ns resolution [13]) were used for the thermal mapping. These TIM techniques are based on monitoring temperature -induced changes in silicon refractive index from the device backside.…”

Section: Devices and Measurement Conditionsmentioning

confidence: 99%

“…Infrared thermography and transient interferometric mapping (TIM) method have previously been used for investigation of temperature distribution in DMOS transistors under single shot [8,9] or repetitive stress [6,7] conditions. On the other hand, thermal simulation tools have been used to optimize thermal design of the devices and system in package [10,11].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Bychikhin

Haberfehlner

Rhayem

et al. 2010

Microelectronics Reliability

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Section: Devices and Measurement Conditionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Bychikhin

Haberfehlner

Rhayem

et al. 2010

Microelectronics Reliability

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“…Therefore, a bipolar transistor is suitable for implementing analog functions, and a CMOS transistor is used in low-power digital circuits. Recently, there has been a growing demand for power chips that use a new bipolar-CMOS-DMOS (BCDMOS) process that can significantly improve device performances and decrease chip size by putting both analog and digital functions onto a single chip in very-large-scale integration (VLSI) systems [1]- [3]. The chip contains both laterally diffused metal-oxide-semiconductor (LDMOS) devices (12 V) for driving power transistors and CMOS devices (3.3 / 5 V) for driving digital high-speed operations [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Development of Low-Vgs N-LDMOS Structure with Double Gate Oxide for Improving Rsp

Jeong¹,

Yi²

2009

Transactions on Electrical and Electronic Materials

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This paper aims to develop a low gate source voltage (V gs ) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 µm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low V gs LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance (R sp ). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

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“…Методика обнаружения локального повышения температуры в приборе с помощью тепловизионных камер (см., например, [1]) имеет пространственное разрешение на уровне десятков микрометров, временное разрешение обычно отсутствует. Метод 2D TIM (transient interference mapping) [2][3][4] использует эффект изменения фазы оптического луча при прохождении через полупроводник и отражении от внешней поверхности прибора. Временное разрешение методики определяется шириной оптического импульса.…”

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Экспериментальные исследования динамики распространения включенного состояния низковольтных лазеров-тиристоров на основе гетероструктур AlGaAs/InGaAs/GaAs

Gavrina¹,

Soboleva²,

Podoskin³

et al. 2019

Письма В Журнал Технической Физики

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A technique is proposed for determining the spatio-temporal dynamics of current in semiconductor heterostructures. This technique is based on the modulation of external radiation during passage through the crystal under study. Approbation of the technique was carried out on semiconductor laser-thyristor based on AlGaAs/ InGaAs/GaAs heterostructures. The experimental results are in a good qualitative agreement with previous measurements of the spatio-temporal dynamics in the laser-thyristor.

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Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system

Cited by 12 publications

References 16 publications

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Development of Low-Vgs N-LDMOS Structure with Double Gate Oxide for Improving Rsp

Экспериментальные исследования динамики распространения включенного состояния низковольтных лазеров-тиристоров на основе гетероструктур AlGaAs/InGaAs/GaAs

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