Thermal instability of low voltage power-MOSFETs

Consoli, A.; Gennaro, F.; Testa, A.; Consentino, G.; Frisina, F.; Letor, R.; Magrì, A.

doi:10.1109/63.844518

Cited by 54 publications

(9 citation statements)

References 3 publications

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“…This can lead to excessive temperatures and -in conjunction with electro-thermal coupling -hot spots, cf. [1]- [3], as has been shown by IR measurements for large power devices, see [4]. However, the IR method cannot be applied to advanced BCD technologies if (thick power copper) metallization obscures the device temperature.…”

Section: Introductionmentioning

confidence: 94%

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Pfost

Joos²,

Stecher

2008

2008 20th International Symposium on Power Semiconductor Devices and IC's

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Self-heating can lead to excessive temperatures in large power DMOS transistors, thus restricting their safe operating area (SOA). To explore that limit, the device temperature must be known with sufficient accuracy, which is difficult in advanced BCD technologies. This is because standard measurement methods such as infrared thermography do not show the true device temperature. Also, most (electro-)thermal simulation approaches have not been experimentally verified close to the SOA limits.In this work, a test chip with novel temperature sensors embedded inside the DMOS cell array will be used for accurate measurements of the device temperature. Moreover, a 3-D numerical temperature simulator is extended to correctly consider the temperature-dependent DMOS behavior. Thus, electro-thermal coupling is taken into account while simultaneously calculating the temperatures with high spatial resolution.The validity of the simulator will be demonstrated experimentally by comparison to measurements for temperatures exceeding 500 • C, up to the onset of thermal runaway.

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Section: Introductionmentioning

confidence: 94%

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Pfost

Joos²,

Stecher

2008

2008 20th International Symposium on Power Semiconductor Devices and IC's

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“…They present conduction voltages lower than silicon diodes, but still have voltage drops in the 0.1-0.2 V range. Today, low-voltage MOSFETs (metal oxide semiconductor field effect transistor, [8,9]), with a typical drain-source resistance of few milliohms, can present voltage drops lower than millivolts for the considered application. They are often referred to as 'synchronous rectifiers'.…”

Section: Harvesting Circuitmentioning

confidence: 99%

A power harvester for wireless sensing applications

Casciati

Rossi

2007

Struct. Control Health Monit.

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In many implementations of structural monitoring, wires connecting the sensors in a chain or in a network are not allowed. Furthermore, most of the sensors are supposed to work just after a triggering event, so that they only absorb energy during a limited number of short working periods. Nevertheless, power harvesting is the weak link in conceiving a fully wireless architecture. The overall problem is discussed throughout this paper and solutions for specific civil engineering environments are pursued.

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“…Moreover, the fast turn-off of only a portion of the device forces the remainder to drive a large amount of current during switching. This results in a dramatic current density increase in the slowest parts of the device that will be referred to as "hot spots" [1][2][3][4][5]. This phenomenon is much more pronounced when the device is operated at higher switching frequencies because the current imbalance between the fastest and slowest elementary transistor cells becomes proportionally larger.…”

Section: Introductionmentioning

confidence: 96%

Effect of layout parasitics on the current distribution of power MOSFETs operated at high switching frequency

et al. 2006

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The internal electrical characteristics of an 800-V 9-A 0.7-silicon power MOSFET are investigated using a distributed modelling approach. A cad tool has been developed to automatically extract layout parasitics and create an equivalent spice-like netlist of the device under investigation. The distributed model is employed to investigate the performance of the device during a turn-off switching at different values of the gate fall time. Simulations show that reducing the gate fall time contributes to increase the internal current imbalance leading to current density overshoots, referred to as hot spots. Moreover, faster switching operation forces current density to crowd towards the slowest parts of the device which in turn degrades the overall device ruggedness. These results demonstrate that the proposed modelling approach allows accurate simulation of the internal current distribution identifying the regions where hot spots are more likely to occur.

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Thermal instability of low voltage power-MOSFETs

Cited by 54 publications

References 3 publications

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

A power harvester for wireless sensing applications

Effect of layout parasitics on the current distribution of power MOSFETs operated at high switching frequency

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