Thermal modeling and experimental characterization of the C4/surface-mount-array interconnect technologies

Thermal Management of On-Chip Caches Through Power Density Minimization

“…The heat flow in the package depends on many parameters such as geometry, flux source and placement, package orientation, next-level package attachment, heat sink efficiency, and method of chip connection. In this paper, we consider a typical flip-chip C4 package adapted from a model by Kromann [14] as shown in Figure 3. Most of the heat generated is conducted upwards through the silicon to the thermal paste, aluminum cap, heat sink attach, and heat sink, then convectively removed to the ambient air.…”

“…The thermal resistances of the silicon, the aluminum cap, and the heat sink attach is small, and their contribution to the temperature drop can be omitted for a first-order analysis [14]. Hence, the junction-to-ambient thermal resistance can be expressed as k heat te thermalpas ja sin (5) It is shown in [14] that the thermal paste resistance is reduced as the chip area increases.…”

“…Hence, the junction-to-ambient thermal resistance can be expressed as k heat te thermalpas ja sin (5) It is shown in [14] that the thermal paste resistance is reduced as the chip area increases. This is because a thermal resistance can be written as [5] A R th (6) where R th is the unit thermal resistance, and A is the cross-sectional area.…”

“…Convective thermal resistance of the heat sink, heatsink is affected less by the chip area since the heat is usually spread out more uniformly (using a heat spreader) before it reaches the heat sink. However, in case of adapting an advanced fan heat sink as it is commonly done in today's technology, the heat sink resistance becomes small enough that the thermal paste resistance takes up the majority of the total junction-toambient thermal resistance (more than 60%) [14]. Therefore, reducing the power density of the chip can significantly lower the junction temperature.…”

Area optimization for leakage reduction and thermal stability in nanometer scale technologies

“…The heat generated from a chip is dissipated through the silicon substrate, and the cooling system in the package. The heat flow in the package is a function of many parameters such as geometry, flux source and placement, package orientation, next-level package attachment, heat sink efficiency, and method of chip connection [15]. In this paper, we consider a typical flip-chip C4 package adapted from models by Kromann in [15] as shown in Figure 3.…”