Thermal noise modeling for short-channel MOSFETs

Triantis, D.P.; Birbas, Alexios; Kondis, D.

doi:10.1109/16.543032

Cited by 134 publications

(53 citation statements)

References 8 publications

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“…• Chen and Deens' model Before Chen and Deen proposed their model in 2002 (Chen & Deen, 2002), all of the theories (Triantis, Birbas & Kondis, 1996;Klein, 1999;Scholten et al, 1999;Jin, Chan & Lau, 2000;Park & Park, 2000;Knoblinger, Klein & Tiebout, 2001) attributed the enhanced channel thermal noise to the hot carrier effect, following the similar arguments for the excess noise in field-effect transistors (Klassen, 1970;Baechtold, 1971;Takagi & Matsumoto, 1977;Jindal, 1986). Chen and Deen, however, considered the channel length modulation (CLM) effect and proposed the spectral density of the channel noise as (Chen & Deen, 2002) where E crit is the critical electrical field, Q inv is the total inversion charge in the gradual channel region, and L elec is the electrical channel length of the device (L elec = L eff − ΔL, where ΔL is the channel length of the velocity saturated region).…”

Section: Thermal Noise Modelingmentioning

confidence: 99%

Thermal Noise in Modern CMOS Technology

Chen¹

2010

Solid State Circuits Technologies

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Section: Thermal Noise Modelingmentioning

confidence: 99%

Thermal Noise in Modern CMOS Technology

Chen¹

2010

Solid State Circuits Technologies

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“…This hot carrier effect is not exactly known [12]. For simple noise modeling, the general relation between c T and electric field has been assumed as (10) where η depends on the type of scattering mechanism [13]. When acoustic deformation potential scattering dominates, η has a numerical value of 2 for silicon.…”

Section: Strong Inversion Regionmentioning

confidence: 99%

A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

Yu¹

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.Index Terms-Unified channel thermal noise model, all region noise model, interpolation approach, BSIM3 noise model, short channel effect

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“…It has been experimentally shown [148] that for 0.7-µm devices the value of γ ranges from 2.5 to 9, depending on the bias conditions. Analytical models for γ have been proposed in [149] and [150]unfortunately, they are too complicated for hand calculations. In general, however, γ increases as the gate-source voltage decreases and/or as the drain-source voltage increases.…”

Section: Noisementioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Thermal noise modeling for short-channel MOSFETs

Cited by 134 publications

References 8 publications

Thermal Noise in Modern CMOS Technology

Thermal Noise in Modern CMOS Technology

A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

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