Thermal performance analysis of GaN nanowire and fin-shaped power transistors based on self-consistent electrothermal simulations

Kamrani, Hamed; Feng, Yuqing; Frank, Kristian; Strempel, Klaas; Fatahilah, Muhammad Fahlesa; Wasisto, Hutomo Suryo; Römer, Friedhard; Waag, A.; Witzigmann, Bernd

doi:10.1016/j.microrel.2018.10.007

Cited by 2 publications

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“…In quantum engineered transistors and logic applications, this vertical method also gives a new strategy towards higher performance and integration of p - and n -channel transistors 17,18 . From our point of view, the vertical 3D architecture has become more attractive because it provides more advantages: (1) it can minimize the current collapse, thanks to the absence of surface-related trapping phenomena; (2) the gate length ( L ) is not limited by lithography process; (3) gating technology can be flexibly designed (e.g., wrap around gate); (4) vertical parallel current paths and collection can be obtained on a small footprint for high scalability; (5) better thermal performance, at which the maximum temperature is close to top part of NWs, brought potential to achieve more power density; and (6) contrary to lateral devices, where breakdown voltage scales with area (and cost), in vertical devices the breakdown voltage is only dependent on the thickness/properties of the epitaxial stacks 13,19–25 .…”

Section: Introductionmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

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This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

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