Thermal stability of CoSi₂layers implemented in a silicon-on-insulator substrate

Abstract

A silicon-on-metal-on-insulator substrate, consisting of a top Si layer, a buried CoSi 2 layer and a buried SiO 2 layer on a Si (1 0 0) substrate was formed using Co silicidation, wafer bonding and wafer splitting. It is shown that the buried silicide layers in this structure exhibit a much higher thermal stability than surface layers. Resistivity measurements and cross-sectional transmission electron microscopy investigations revealed that buried CoSi 2 layers withstand furnace anneals at 1000 • C up to 2 h, while surface CoSi 2 layers started to degrade after 10 min anneals at 1000 • C. The proposed substrate is most useful for BiCMOS applications.

Ultrafast time-domain spectroscopy based on high-speed asynchronous optical sampling

“…Such substrates are employed in a Bipolar Complementary Metal Oxide Semiconductor ͑BiCMOS͒ process. 14 Figure 5 shows the modulations due to multiple reflected acoustic pulses within the top layer extracted from the exponentially decaying thermal background. The reflections are equally spaced and exhibit characteristic sign changes after each reflection from a Si-air interface.…”

Challenges of Smart System Integration

“…Different concepts are being worked on that imply the covering of the micro mechanical structure by using different bonding methods first and the interconnection and wiring of electrical signals as well. One main goal of our work is the development of packaging methods for any micro machined structures with low temperature approaches, which provides a hermetic protection of these structures against environmental conditions (2,3). This is important as the process temperature during the bonding process is often the limiting factor especially in the integration of new materials, such as micro systems for medical applications, which consist mostly of temperature sensible components.…”

Performance Analyses of Planar Schottky Barrier MOSFETs with Dual Silicide Layers at Source/Drain on Bulk Substrates and Material Studies of ErSix/CoSi2/Si Stack Interface*

“…We apply low barrier height for the top contact, SBH t = 0.2 eV, (e.g., ErSi 1.7 with 0.28 eV for electron), [16,17] and high barrier for the bottom contact, SBH b = 0.6 eV, (e.g., CoSi 2 with 0.64 eV for electron). [18] For SBFETs, the silicon channel thickness 𝑑 si is much thinner than 𝑑 tot , and the barrier height at source/drain contact equals SBH t . The supply voltage 𝑉 dd is set to be 0.5 V. The default gate work function is 4.18 eV, and work function engineering is also used for studying the influence of barrier height.…”