Thermal Stress Analysis of a PQFP Moulding Process: Comparison of Viscoelastic and Elastic Models

Park, Joo Hyuk; Kim, Jang Kyo; Lee, S. W. Ricky; Tong, Penger; Chan, P.C.H.

doi:10.4028/www.scientific.net/kem.145-149.1127

Cited by 17 publications

(6 citation statements)

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“…A comparison of the stress levels at the bottom die corner between the two models is plotted in Figure 13. The stress level predicted by the elastic model was more than four times higher than the viscoelastic model, which agreed with the conclusions in our previous study on plastic quad flat pack (PQFP) packages [4]. It is also interesting to note that the extent of stress relaxation in the The accumulated creep strain profiles in the corner solder bump are compared between the two models in Figure 14.…”

Section: Residual Stresses and Creep Strainssupporting

confidence: 87%

“…It is shown previously [3][4][5][6][7] that the viscoelastic assumption for polymeric encapsulants made in theoretical studies of electronic packages in general provided better agreement with experimental results obtained from the stress chip measurement than the elastic assumption. Incorrect simplifying assumptions for the material behaviour may often result in erroneous conclusions due to the over-or underestimate of imposed stresses/strains.…”

Section: Introductionmentioning

confidence: 86%

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Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

Sham

Kim

Park

2007

Computational Materials Science

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The reliability and mechanical performance of electronic integrated circuit (IC) package is studied based on the finite element analysis. The flip chip on board (FCOB) package -one of the most current plastic encapsulated IC packages -consists of a die, solders, a printed circuit board and underfill resin encapsulated between the die and PCB, which is subjected to a typical thermal cycle experienced during the manufacturing process. The effects of viscoelastic properties of underfill resin on mechanical responses and residual stresses of FCOB packages are specifically studied and the results are compared with those obtained for a thermo-elastic underfill resin. The viscoelastic properties of underfill resin are characterized using the time-temperature superposition (TTS) technique. Both the rigid and flexible PCB substrates are considered.It is found that the elastic model underestimates significantly both the thermal stress and the accumulated creep strain in the solder joints, whereas it overestimates the stress concentrations in the underfill fillet around the die corner than the viscoelastic model. When the package is subjected to an extended dwell time at an elevated temperature, a moderate loss of mechanical coupling between the die and organic substrate is expected due to the relaxation of underfill resin. The implication is that the viscoelastic nature of underfill material should be properly taken into account if the failure of solder joints and the lifetime of the package are to be accurately estimated. This study shed an insight into the importance of correct material property inputs in the design and theoretical studies of plastic packages.

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Section: Residual Stresses and Creep Strainssupporting

confidence: 87%

Section: Introductionmentioning

confidence: 86%

Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

Sham

Kim

Park

2007

Computational Materials Science

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“…Where 0 the zero-shear-rate viscosity, K * W the critical shear stress, n the power law index, D g the degree of cure at gel point, 1 C and the two fitted constants, A an exponential fitted constant, and b T a temperature-dependent fitted constant. The detail of the flow model could be found in Ref.…”

Section: Flow Analysismentioning

confidence: 99%

“…In this study, serious warpage will not proceed to the next manufacture process. In general, different coefficients of thermal expansion (CTE) values between constitutive materials were considered as the main reasons for warpage [1] [2] [3]. In recent years, there are more evidences showing that it is not sufficient to predict the amount of warpage of IC packages if considering only the CTE value difference between constitutive materials [4] [5] [6] [10].…”

Section: Introductionmentioning

confidence: 99%

Warpage simulations with P-V-T-C equation and experiments of fan-out wafer level package after encapsulation process

Deng

Hwang

Lee

et al. 2010

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference

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Wafer level packaging is the technique that encapsulates integrated circuit on the wafer directly and different from the traditional IC package. Comparing with the traditional IC package, wafer level chip scale packaging has several advantages such as: smaller package size (reduce area and thickness), lighter weight, more fabricate simply, better electric performance and cost down. Therefore, the wafer level package is suitable for cell phones, notebooks, handheld computers and digital cameras. In addition, the wafer level package can integrate wafer manufacture, encapsulation and test that simplifies the all production processes. The fan-out wafer level package discussed here has the flip chip form which uses thin-film redistribute then uses solder bump to connect the package to the printed wiring board directly. Liquid compound was used for the encapsulation process. Because the thickness of the fan-out wafer level package is thinner than traditional IC package, so the fan-out wafer level package produced more serious warpage. Warpage plays an important role during integrated circuit encapsulation process and the too large amount of warpage will not proceed to the next manufacture process in this study. Previous researchers had focused on warpage analysis with thermal-induced shrinkage and the cure-induced shrinkage was neglected. However, more and more studies indicated that the prediction of warpage only according to CTE (Coefficient of Thermal Expansion) was not able to accurately predict the amount of warpage in IC packaging. This study used an approach considering both cureand thermal-induced shrinkage during encapsulation process was presented to predict the amount of warpage. The cureinduced shrinkage was described by the pressure-volumetemperature-cure (P-V-T-C) equation of the liquid compound. The thermal-induced shrinkage was described by the coefficients of thermal expansion of the component materials. The liquid compound properties were obtained by various techniques: cure kinetics by differential scanning calorimeter (DSC), cure induced shrinkage by P-V-T-C testing machine. These experimental data were used to formulate the P-V-T-C equation.In this study, fan-out wafer level package was used for the simulation. The simulation results were verified with experiments. It showed that the approach of considering both thermal and cure/compressibility effects could better predict the amount of warpage for fan-out wafer level package. The P-V-T-C equation was successfully implemented and verified that warpage was governed by both thermal shrinkage and cure shrinkage. The amount of warpage after molding could be accurately predicted with this methodology. The simulation results showed that cure shrinkage of liquid compound was the dominant factor for package warpage after encapsulation.

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“…For fan-out packages, serious warpage will not let the package proceed to the next manufacturing process. In general, different values of the coefficient of thermal expansion (CTE) between the constituent materials are considered as the main reasons for warpage [1]- [3]. In recent years, there has been significant evidence showing that it is not sufficient to predict the amount of warpage of IC packages by considering only the CTE value difference between constituent materials [4]- [6], [17].…”

Section: Introductionmentioning

confidence: 99%

Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process

Deng

Hwang

Lee

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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A waferlevel package (WLP) that has a flipchip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure-and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure-volumetemperature-cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry-and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation.Index Terms-Fan-out, pressure-volume-temperature-cure (PVTC), warpage, wafer level package.

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Thermal Stress Analysis of a PQFP Moulding Process: Comparison of Viscoelastic and Elastic Models

Cited by 17 publications

References 0 publications

Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

Warpage simulations with P-V-T-C equation and experiments of fan-out wafer level package after encapsulation process

Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process

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