Thermionic-field emission from interface states at grain boundaries in silicon

IEEE Electron Device Lett.

Chan

2001

The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate.

Section: Effects Of Grain Boundaries Orientation On Device Perfomentioning

confidence: 98%

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

Singh

IEEE Electron Device Lett.

Chan

2001

“…This mechanism has been shown to account for the dependence of I OFF on V g and on V ds . 19,20 The latter dependence is clear in Fig. 7 as we compare I ds vs. V g characteristics for V ds ϭ ϩ10 V and ϩ0.1 V, whereas the former dependence is also seen in the same figure for Ϫ10 V < V g < 0 V where the leakage current increases steadily with the negative gate voltage.…”

Section: Resultsmentioning

confidence: 62%

Crystallization of a‐Si:H on Glass for Active Layers in Thin Film Transistors: Effects of Glass Coating

Fonash

Awadelkarim

et al. 1999

J. Electrochem. Soc.

Polycrystalline silicon (poly-Si) thin films with large grains and low defect density are promising materials for thin film transistors (TFTs) for use as the pixel switching elements as well as for use as the driving elements in active matrix liquid crystal displays. For these applications it is necessary to fabricate TFTs on glass substrates and, therefore, a number of low temperature processes are currently being explored. 1,2 Laser and solid-phase crystallization of amorphous silicon (a-Si) precursors which are prepared from lowpressure chemical vapor deposition (LPCVD), sputtering, or plasma-enhanced chemical vapor deposition (PECVD) as well as the direct deposition of poly-Si are some promising approaches. 3,4 The solid-phase crystallization (SPC) approach by furnace annealing or rapid thermal annealing (RTA) has several advantages over other poly-Si fabrication processes. These advantages include smoother surfaces, better uniformity, and, when compared to laser crystallized poly-Si, higher throughput. 5 In this paper, we first report on the SPC of PECVD a-Si:H films deposited on either bare glass or silicon nitride (SiN x ) coated glass substrates. Our investigation utilized precursor films deposited at a series of temperatures. In order to examine SPC kinetics in detail, we used conventional furnace annealing at 600ЊC in N 2 ambient for the SPC step. Since the drive is to lower temperature processing and since silicon nitride (SiN x ) can be used as an effective diffusion barrier layer, 6,7 it is important for the understanding of the low temperature production of TFTs to investigate the effects of precursor deposition and substrate coating on a-Si:H crystallization and on microstructural qualities of the resulting poly-Si thin films. Upon the completion of detailed material characterization of the deposited a-Si:H films and their corresponding crystallized poly-Si, we then fabricated n-channel poly-Si TFTs on these same films. Transistor parameters were measured, and transistor characteristics were correlated with material properties of the poly-Si films. ExperimentalPolycrystalline silicon material preparation and characterization.-The a-Si:H films investigated in this study were PECVD deposited from H 2 -diluted silane (SiH 4 ) gas (4:1) in an Applied Kamatsu system. These a-Si:H films were deposited on either bare Corning 7059 glass substrates or Corning 7059 glass substrates coated with 100 nm thick silicon nitride. The SiN x layers were also deposited by PECVD in the same system from silane, ammonia (NH 3 ), and nitrogen (N 2 ) gases without exposure to air. For a-Si:H films on nitride-coated substrates the a-Si:H layers were deposited following the deposition of SiN x layers. Before loading in the PECVD tool, the glass substrates were cleaned using detergent and DI water then dried in hot air. The substrate temperature during deposition was varied between 150 and 320ЊC, and the deposition rate was kept constant at 10 Å/s. The thicknesses of the deposited a-Si:H films were of the order of 1000 Å. The...

“…Currently, the most currently accepted mechanism for IoFF generation is reported to be associated with band-to-band tunneling via grain boundary and/or impurity trapping states near the drain [5][6][7]. In terms of this mechanism, IoFF in our TFTs occurs when the poly-Si surface below the gate oxide is accumulated and it arises from grain boundary/impurity trapassisted field emission between the accumulation layer and the drain.…”

Section: Discussionmentioning

confidence: 96%

“…TFTs have been the subject of several studies [5][6][7]. Currently, the most currently accepted mechanism for IoFF generation is reported to be associated with band-to-band tunneling via grain boundary and/or impurity trapping states near the drain [5][6][7].…”

Section: Discussionmentioning

confidence: 99%

Correlation of Performance and Hot Carrier Stress Reliability of Polycrystalline Silicon Thin-Film Transistors With Substrates and Substrate Coating

Awadelkarim

1998

MRS Proc.

We report on the performance and hot carrier stress (HCS) reliability of n-channel poly-Si TFTs fabricated on bare or SiO 2 -coated low-alkali glass, or fused silica substrates. Low-pressure chemical vapor deposited (LPCVD) SiO 2 films with different thicknesses are used as impurity diffusion barrier layers. We have found that the performance and HCS reliability of n-TFTs on the SiO 2 -coated glass are superior to those of n-TFTs on bare glass, and comparable to those of TFTs on fused silica. We also explore the impact of the SiO 2 coating thickness on the performance and HCS reliability of the TFTs. The HCS reliability of the TFTs on SiO 2 -coated glass substrates is observed to depend on the SiO 2 coating thickness. This is explained in terms of a phenomenological model which involves impurity and grain boundary traps.