A fundamental limit for the supply voltage of conventional field-effect transistors is the long high-energy tail of the Boltzmann distribution of the carrier population at the source junction, which requires a gate voltage at least 60 mV to change one decade of current. Here 2D semiconductors are adopted as channel materials and hafnium zirconium oxide (HZO) as negative capacitance (NC) gate stack to realize low-power complementary logic inverter. With HZO/Al 2 O 3 NC gate stack, the 2D semiconductor field-effect transistor (FET) shows an average subthreshold slope less than Boltzmann limit (as low as 18 mV dec −1) at room temperature for both forward and reverse gate voltage sweeps, which allows to reach the same ON-state current at a lower V dd without increasing the OFF-state current. The drain current can be modulated by 5 × 10 4 within 220 mV, still exhibiting average SS below 60 mV dec −1. By constructing van der Waals contact to improve the charge injection and control the carrier type, unipolar p-type WSe 2 FET with reduced hole Schottky barrier height is achieved. The complementary inverter with MoS 2 and WSe 2 NCFETs shows the power consumption of 68 pW.

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Steep-slope p-type 2D WSe2 back-gated field-effect transistors (FETs) are realized by using van der Waals Pt-WSe2 contact and HfZrO2/Al2O3 as the dielectric layer. The van der Waals Pt-WSe2 contact is free from disorder and Fermi level pinning and decreases the sub threshold slope. The WSe2 NCFET with van der Waals contact shows low subthreshold slope for both forward and reverse gate voltage sweep (the minimum SSforward = 18.2 mV/dec and SSreverse = 44.1 mV/dec) with a hysteresis as small as 20 mV at sub threshold region.