A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current ( 1 A) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage ( DO ) with large-size pass transistor and ultra-low can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18-m standard CMOS process and occupies 0.09 mm 2 . The LDO regulator can deliver 50-mA load current at 1-V input and 100-mV DO . It only consumes 1.2 A and is able to recover within 4 s even under the worst case scenario.Index Terms-High slew rate, low-dropout (LDO) regulator, low-quiescent current, tail current.

In order to be useful for mobile systems, the switching frequencies of modern buck converters (BCs) are in the MHz-or even GHzrange to enable the use of compact off-chip inductors and capacitors [1], or even on-chip Ls and Cs [2]. However, such high switching frequencies increase both the switching loss and the gate-drive loss, and degrade BC light-load efficiency since these losses are independent of load current. Pulse-frequency modulation (PFM) is known to improve light-load efficiency by scaling the switching frequency with the load current so that the switching loss and the gate-drive loss are reduced with decreased load current. However, PFM makes the BC output spectrum change with the load current. This unpredictable spectrum causes supplyintegrity to be an issue in mobile systems where different spectrum-sensitive circuits, such as communication ICs, are often used. Recently, the light-load efficiency of BCs operating at a constant switching frequency in MHz range have been improved [3,4]. However, the methods used only reduce the gate-drive loss, which is the power required to switch the power PMOS and NMOS transistors (M P and M N in Fig. 24.4.1), but not the switching loss, which is the power needed to switch the switching node (V X in Fig. 24.4.1). BC light-load efficiency can only be greatly improved when these two losses are simultaneously reduced.In this work, an auto-selectable-frequency pulse-width modulator (ASFPWM) is introduced to enable BCs to use compact off-chip Ls and Cs and to minimize both the switching loss and the gate-drive loss without causing a supply-integrity problem. ASFPWM automatically selects the BC switching frequency (f S ) based on its load current (I LOAD ). f S is chosen from a set of pre-defined frequencies, which are all binary-weighted multiples of a fundamental frequency f D (e.g., f S = 2 i f D , where i = 0...N, and N is a finite positive integer). As shown in Fig. 24.4.1, the spectral components of the output, V OUT (f), of a BC with ASFPWM are all located at multiples of f D regardless of I LOAD . Therefore, the spectrum of such a BC is as predictable as one with pulse-width modulation (PWM) at f D and, even though f S is scaled with I LOAD , supply-integrity is not a problem in ASFPWM. Furthermore, the light-load efficiency is greatly improved as the switching loss and gate-drive loss are simultaneously reduced with decreasing I LOAD . Compact off-chip Ls and Cs can be used by designing the maximum f S of ASFPWM to be in the MHz range (e.g. [f S ] max = 2 N f D ). Figure 24.4.1 shows the block diagram of a BC with ASFPWM; it consists of a frequency selection unit (FSU), a control unit (CU), and an adaptive dead-time unit (ADTU). The FSU automatically determines f S by comparing I LOAD with different thresholds (I LOADTH_i , where i = 0...N); each I LOADTH_i corresponds to a particular switching frequency (e.g., 2 i f D ). The FSU produces the clock signal (V CLK ) based on the selected f S . The CU regulates the BC output (V OUT ) and keeps it close to the refer...

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