A High Slew-Rate Push&amp;#x2013;Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

Man, Tsz Yin; Mok, Philip K. T.; Chan, Mansun

doi:10.1109/tcsii.2007.900347

Cited by 196 publications

(105 citation statements)

References 7 publications

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“…1, the basic structure of this ultra-fast capacitor-less LDO is similar with [13] focusing on dynamic biasing. It is constructed by two differential commongate transconductance cells, a voltage buffer, a current-summation circuit and an additional SRE circuit.…”

Section: Design Of the Proposed Circuitsmentioning

confidence: 99%

“…However, by making the sizes of these transistors small, the parasitic capacitances are set small and the time delay can be ignored. In addition, transistors M 14 and M 15 are used to prevent the noise of N 1 and N 2 from coupling to the gate of the power transistor when transistors M 13 and M 16 are turned on.…”

Section: ) Sensitivity To Supply Voltagementioning

confidence: 99%

“…The response time of the SRE circuit is determined by the time required to turn on or turn off drive transistors M 13 and M 16 when an output voltage spike ΔV is applied to the DPP SRE circuit. During the positive (negative) output slewing, transistor M 12 (M 10 ) is in the saturation region.…”

Section: ) Optimal Sizing Of Drive Transistorsmentioning

confidence: 99%

“…For example, the buffer stage is adaptively biased as shown in [10], where the increase in current in the buffer stage aids the circuit by pushing the parasitic pole associated with parasitical capacitors at the gate of power transistors to higher frequencies and by increasing the current available for slew-rate conditions; one more choice is used at the input stage in [11] and [12] to simultaneously extend both slewing and bandwidth. Another more current-efficient way is to utilize dynamic biasing technique where more bias current is adopted only at the transient instant when the output current is changed [13]. Based on this idea, the capacitive coupling and dynamic charging method is reported lately, which is very promising in increasing circuitry response speed while keeping static power consumption low.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Ming¹,

Zhou²,

Zhang³

2012

VLSI-SoC: Advanced Research for Systems on Chip

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Abstract.A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this chapter. It makes use of an adaptive biasing common-gate amplifier to extend loop bandwidth of the LDO at heavy loads greatly. Also, the dynamic push-pull (DPP) slew-rate enhancement (SRE) circuit based on capacitive coupling detects rapid voltage spikes at the output to provide an extra current to charge and discharge the large gate capacitance of the power transistor momentarily. The proposed circuit has been implemented in a 0.35µm standard CMOS process. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 10μA quiescent current at no-load condition and is able to recover within 0.8µs even under the maximum load current change.

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Section: Design Of the Proposed Circuitsmentioning

confidence: 99%

Section: ) Sensitivity To Supply Voltagementioning

confidence: 99%

Section: ) Optimal Sizing Of Drive Transistorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Ming¹,

Zhou²,

Zhang³

2012

VLSI-SoC: Advanced Research for Systems on Chip

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“…The quality of the power supply in portable electronic systems can be efficiently addressed with point-of-load distributed power delivery [1,2], which requires the on-chip integration of multiple power supplies. Several low-dropout (LDO) regulators suitable for on-chip integration have recently been fabricated [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17], exhibiting fast load regulation and high current efficiency. Due to these characteristics, the LDO is a key component in on-chip power management.…”

Section: Introductionmentioning

confidence: 99%

Distributed LDO regulators in a 28 nm power delivery system

P.-Vaisband

Price

Köse

et al. 2015

Analog Integr Circ Sig Process

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A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power efficient voltage regulation, exhibiting 64 ps response time of the regulation loop and 99.49 % current efficiency. An adaptive compensation network is also employed within the distributed power delivery system to maintain a stable system response within 25 to 105°C and 10 % voltage variations with a capacitive load of more than 472 pF. No off-chip capacitors are required. Under a 788 mA load current step with 5 ns load edge, the power delivery system exhibits less than 15 % voltage droop for nominal input and output voltages, and a minimum dropout of 0.1 V. Each of the LDO regulators with the adaptive networks and bias current generator occupies 85 lm 9 42 lm in a 28 nm CMOS process. All of the test measurements are performed in a distributed power delivery system of six on-chip LDO regulators within a commercial high performance portable device. The proposed system is the first successful silicon demonstration of stable fully integrated parallel analog LDO regulators.

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Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

Saberkari

Qaraqanabadi

Shirmohammadli

et al. 2015

Circuit Theory & Apps

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SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

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A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

Cited by 196 publications

References 7 publications

A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Distributed LDO regulators in a 28 nm power delivery system

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

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