Thermo-Mechanical Analysis of Thru-Silicon-Via Based High Density Compliant Interconnect

Arunasalam, Parthiban; Zhang, Fan; Ackler, Harold D.; Sammakia, Bahgat

doi:10.1109/ectc.2007.373943

Cited by 9 publications

(10 citation statements)

References 9 publications

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“…The coefficient of thermal expansion (CTE) of copper (∼ 17.5μ/ • C) is much higher of the silicon CTE (∼ 2.5μ/ • C) [6]. Due to thermal cycling and local thermal expansion mismatch between the copper and silicon substrate the stacked die has the delimitation potential in the interface of the TSV, dielectric, substrate, and grid [19]. λ T M , effective stress and thermo-mechanical failure rate of the TSV increases as either the TSV diameter reduces or density reduction [6].…”

Section: B Stacked Die Thermo-mechanical Reliabilitymentioning

confidence: 99%

3D stacked power distribution considering substrate coupling

Shayan

Zhang

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed. The analytical model considers the impact of the substrate coupling between the TSVs and layers grid. A frequency domain based analysis flow is introduced to incorporate frequency dependent parasitics. The design of a reliable power distribution network is formulated as an optimization problem to minimize power noise under reliability and electro-migration constraints. Experimental results demonstrate the efficacy of the problem formulation and solution technique.

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Section: B Stacked Die Thermo-mechanical Reliabilitymentioning

confidence: 99%

3D stacked power distribution considering substrate coupling

Shayan

Zhang

et al. 2009

2009 IEEE International Conference on Computer Design

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“…Since these interconnects were defined with photolithography and dry-etch chemistry, the exact beams shown in Figure 1 can potentially be spaced at 30 ȝP (laterally) by 155 ȝP ORQJLWXGLQDOO\ SLWFK ZLWh a new mask, bringing the total number of compliant interconnects on a 1 cm 2 chip to beyond 21000. Detailed fabrication of STAC interconnect can be found in the work done by Arunasalam et al [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Modeling heat transport in thermal interface materials enhanced with MEMS based microinterconnects

Zhang

Arunasalam

Murray

et al. 2008

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Thermal management of device level packaging continues to present many technical challenges. In the typical chip heat sink assembly, the highest resistance to heat flow comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper will introduce a unique TIM enhanced with ultrahigh density wafer level thin film compliant interconnects named Smart Three Axis Compliant (STAC) interconnects. The MEMS technology based STAC interconnect is directly fabricated onto a silicon wafer and embedded into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Numerical and analytical analyses of the thermal conduction in the TIM embedded with STAC interconnects are performed. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications.Parametric studies are conducted to examine the thermal conductivity of the microinterconnect enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. For the modeling, a periodic element model of chip-TIM configuration with top heat sink is developed and maximum temperatures are determined in order to evaluate the conductive effect of the microinterconnect. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multi-chip stack package with and without through-silicon-vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using microinterconnects structured TIM is proposed.

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“…Two contact modes are used in these structures: soldered contact and sliding contact. Soldered contacts use solder on the MEMS based compliant interconnect structure to make connection and have been used on a number of MEMS structures including microsprings [3]- [5], microhelix structure [6] and sea of leads [7]. Soldered contacts provide good reliability and low electrical resistance.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of Double Helix Structures for Compliant and Reworkable Electrical Interconnects

Pfeiffenberger

Ellis

et al. 2014

J. Microelectromech. Syst.

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Microelectromechanical systems (MEMS)-type double helix chip-level electrical interconnect structures are fabricated and characterized in this paper. Due to their springlike structure, double helix interconnects have the potential to provide large mechanical compliance to compensate for nonidealities, such as nonplanarity and thermal expansion mismatch between silicon chips and substrates. A double helix configuration provides for structures with a high volumetric density of conductor for enhanced current carrying capability. The fabrication process is compatible with wafer-level fabrication and packaging. Instead of using solder to form semipermanent interconnections, the double helix interconnects use pressure to make electrical connection and provide sufficiently low resistance (∼35 ± 15 m ). Large arrays of double helix structures have been fabricated and characterized with excellent yield. The mechanical and electrical models of the structures are presented. Reworkability tests were performed and the structures show a consistent resistance over 50 remating cycles. [2013-0296] Index Terms-Microelectromechanical systems (MEMS), flip chip packaging, interconnect, reworkability.

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Thermo-Mechanical Analysis of Thru-Silicon-Via Based High Density Compliant Interconnect

Cited by 9 publications

References 9 publications

3D stacked power distribution considering substrate coupling

3D stacked power distribution considering substrate coupling

Modeling heat transport in thermal interface materials enhanced with MEMS based microinterconnects

Fabrication and Characterization of Double Helix Structures for Compliant and Reworkable Electrical Interconnects

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