Characterisation results of the complex permittivity of select dielectric cooling fluids at room temperature and over a broad frequency range found using a low-loss printed circuit board microstrip ring resonator technique are presented. ANSYS HFSS, a finite-element full-wave electromagnetic simulation environment, was used to fit the simulated insertion loss to the calibrated measurements of the microstrip ring resonator in air and submerged in different dielectric fluids. The resulting frequency-dependent relative permittivity and loss tangent are provided up to 50 GHz for three dielectric cooling fluids: 3M™ Novec™ 649, 3M™ Novec™ HFE-7100 and 3M™ Fluorinert™ FC-72.

Microelectromechanical systems (MEMS)-type double helix chip-level electrical interconnect structures are fabricated and characterized in this paper. Due to their springlike structure, double helix interconnects have the potential to provide large mechanical compliance to compensate for nonidealities, such as nonplanarity and thermal expansion mismatch between silicon chips and substrates. A double helix configuration provides for structures with a high volumetric density of conductor for enhanced current carrying capability. The fabrication process is compatible with wafer-level fabrication and packaging. Instead of using solder to form semipermanent interconnections, the double helix interconnects use pressure to make electrical connection and provide sufficiently low resistance (∼35 ± 15 m ). Large arrays of double helix structures have been fabricated and characterized with excellent yield. The mechanical and electrical models of the structures are presented. Reworkability tests were performed and the structures show a consistent resistance over 50 remating cycles. [2013-0296] Index Terms-Microelectromechanical systems (MEMS), flip chip packaging, interconnect, reworkability.

The development of power distribution networks in low temperature co-fired ceramic (LTCC) to deliver power to electronic chips with minimal power loss and/or voltage drop presents real challenges. In the last decade, the power consumption for some applications has increased considerably while the supply voltage has been reduced. A number of designs for low loss power distribution networks were investigated for implementation using low temperature co-fired ceramics (LTCC) technology. This paper discusses the fabrication of power distribution networks (PDNs) using LTCC technology that exhibit sub-milliohm resistance through the use of full tape thickness features and other structures. Experimental data is also presented to support the viability of the approaches presented. The results presented in this paper show that the finite DC conductivity of the silver conductor paste commonly used in LTCC fabrication presents a challenge when attempting to build PDNs with low losses at high current levels. By analyzing a number of scenarios, several approaches are proposed that reduce the DC resistance laterally as well as vertically in a multi-layered LTCC PDN. Experiments and simulations show that the use of various processing techniques to increase the thickness of metallic traces can significantly reduce the lateral DC resistance of the PDN structure. In addition, various via configurations were simulated and fabricated that demonstrate an improvement in the performance of structures that distribute power vertically. Experiments using LTCC to carry a 100 A current were conducted to confirm simulations.

Use of unpackaged die in advanced integrated systems (i.e., 3-D integrated systems) calls for dense interconnection schemes with controlled impedance for high-speed signal routing and minimal impedance for efficient power distribution. We have evaluated a new material set for use in a thin-film-based redistribution layer (RDL) that consists of Asahi Glass AL-X spin-on low-k dielectric polymer and electroplated copper metallization. This technology allows fan-out and interconnection of high-speed signals and power to/from die pads on pitches sufficiently less than 100 μm directly to companion die over short distances or for transition to underlying board metallization for longer transmission distances that may require lower signal loss. This technology is demonstrated using Si wafers onto which the thin-film RDL is fabricated. We have developed and described the fabrication procedures used to construct multiple interconnected layers of AL-X / Cu, which are compatible with standard wafer level packaging (WLP) processes. We have also evaluated the performance of this technology for high-speed digital signal transmission by characterizing frequency parameters (i.e., S parameters) of single-ended and differential strip-line transmission line structures. We have optimized transmission line geometries for transmission of signals at rates greater than 25 Gbps. In addition to high-speed signal redistribution capabilities, we have characterized power redistribution capabilities of this technology. Results of the signal and power integrity measurements and simulations performed in this work are presented.