Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Dao, Thuy; Triyoso, Dina H.; Mora, R.; Kropewnicki, Tom; Griesbach, Brian; Booker, D. J.; Petras, Mike; Adams, V.

doi:10.1109/vdat.2010.5496677

Cited by 5 publications

(4 citation statements)

References 3 publications

(3 reference statements)

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“…As-deposited W exhibits large compressive stresses on the substrate [111], which increase with an increasing TSV diameter and decreasing TSV pitch. Unfortunately annealing at 400°C does not significantly relieve the stress [110].…”

Section: B Sidewall Insulationmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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Section: B Sidewall Insulationmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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“…Via-middle TSVs require a relatively large (12:1 or higher) aspect ratio [14][15][16]20]. Thus, the width of via-middle TSVs is comparable to the width of via-first TSVs whereas the height is comparable to via-last TSVs.…”

Section: Via-middle Tsvmentioning

confidence: 99%

“…For example, in [12] and [29], via-first TSV technology has been investigated with little attention on circuit design implications. Similarly, via-middle TSVs have been discussed in [14][15][16] focusing primarily on process characteristics. The fabrication constraints of the three TSV technologies are also compared in [30].…”

Section: Previous Workmentioning

confidence: 99%

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Satheesh

Salman

2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Electrical Engineering Stony Brook University 2012Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.iii To my dearest parents, Jayashree Krishnamurthy and Satheesh Lakshminarayana.

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“…To reduce the Cu-filling time, a pulse-reverse (PR) current waveform (modified from the pulse current) 11,12) or the addition of inhibitors and accelerators to the plating solution have been reported. 13) As a fundamental solution to overcome these problems, several recent studies have looked into replacing copper with different filling materials, such as tungsten, 14) polymers, 15) alloys, 16) and solders, 17) in an attempt to reduce the thermomechanical stress and shorten the Cu-filling time. He et al 18) suggested a Cu-cored solder for rapid and low-cost processing for TSV fabrication.…”

Section: Introductionmentioning

confidence: 99%

Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

et al. 2015

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The application of Cu-filled through-silicon via (TSV) in 3-D integrated circuit packaging faces several fabrication and reliability issues. In this study, we introduced a Cu-Ni alloy for TSV filling with a high filling speed and a reduced TSV protrusion. In particular, the characteristics of Cu-Ni via protrusions at various annealing temperatures (³200450°C) were investigated with experimental and numerical analysis and compared with Cu-filled vias. High speed Cu-Ni alloy filling into the vias was achieved without any defects by an electroplating process that used a periodic pulse reverse current waveform. The Cu-Ni alloy TSV showed lower via protrusion than the Cu TSV. The simulated protrusion heights of the Cu-Ni vias were in good agreement with the experimental results. The simulation results also indicated that the Cu-Ni TSVs has smaller protrusions than the Cu TSVs. As the annealing temperature was varied from 200 to 450°C, the protrusions increased gradually and became significant at an annealing temperature of 350°C. When the temperature was increased further, the protrusions became larger due to severe creep deformation. The von Mises stress also increased with increasing annealing temperature, and increased substantially at a temperature of 300°C due to the creep effect. In summary, the Cu-Ni alloy TSVs showed smaller protrusions relative to the Cu TSVs. The stress level of the Cu-Ni via was lower than that of the Cu via. These results indicate that the Cu-Ni alloy TSV had advantages in terms of high speed filling and smaller protrusions, demonstrating its promise as an alternative to current Cu TSV technologies.

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Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Cited by 5 publications

References 3 publications

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Lower Protrusion of a Copper-Nickel Alloy in a Through-Silicon via and Its Numerical Simulation

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