Thermometer-to-binary encoder with bubble error correction (BEC) circuit for Flash Analog-to-Digital Converter (FADC)

Bui, Van Hieu; Beak, Seunghyun; Choi, Seung-Hwan; Seon, Jongkook; Jeong, Taikyeong

doi:10.1109/icce.2010.5670690

Cited by 17 publications

(5 citation statements)

References 13 publications

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“…2. For example for a 16 bit ADC , a 16 bit one hot code from the first stage is applied to the leaf nodes in the tree and 4 bit binary output is obtained at the root nodes of trees in the second stage of Fat tree decoder [8]. The signal delay of Fat tree circuit is O(log 2 N) so it is a very fast circuit [10].…”

Section: Cmos Based Fat Tree Decodermentioning

confidence: 99%

Adiabatic technique for fat tree decoder to be used in flash ADCs

Chaudhary

Garg

Niranjan

2015

2015 39th National Systems Conference (NSC)

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Today power dissipation is the most critical problem in Low Power circuits in VLSI design . Adiabatic technique is a technique to reduce power dissipation in digital circuits in which energy stored in a capacitor can be recycled rather than dissipated as heat. In this paper the Fat tree decoder incorporating PFAL i.e. Positive Feedback Adiabatic Logic technique has been simulated using SPICE simulation tool and its power dissipation has been calculated . In this technique , the energy is recovered during recovery phase of the clock supply . The PFAL based decoder has shown a decrease of 50% in the power dissipation as compared to conventional CMOS based decoder within a specific practical range of frequency . Such a low power decoder can be very useful for further use in highly complex designs of A to D and D to A converters.

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Section: Cmos Based Fat Tree Decodermentioning

confidence: 99%

Adiabatic technique for fat tree decoder to be used in flash ADCs

Chaudhary

Garg

Niranjan

2015

2015 39th National Systems Conference (NSC)

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“…In the Gray code, the nearby values (symbols) differ by only one bit, which can help in correcting the faulty bits [30]. The conversion of thermometric code to the Gray code can be conducted by various digital encoders (e.g., a ROM-based encoder [32], a Wallace tree encoder [56], a fat tree encoder [57], and the most widely used multiplexer-based encoder [58][59][60]); more information about the introduced encoders can be found in [30,31,61,62].…”

Section: Rom Encoder and Output Circuitsmentioning

confidence: 99%

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

Sokol,

Galajda,

Saliga

et al. 2024

Sensors

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The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V.

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“…Encoder: We use an encoding module running at 400 MHz and optimized for the FPGA architecture to convert a sample of 140 bits into a binary code. A thermometer-to-binary conversion is employed, with two modifications: the first is an overlapping of the blocks to account for occasionally observed bubbles in the delay line, whereas a bubble occurs when a schematically later bit flips before an earlier one because of an optimized carry block implementation or clock skew [24,25]. The second is a decomposition in three blocks with two decision bits to better map the circuit into the 6-input lookup-tables available in the Spartan 6.…”

Section: Delay Linementioning

confidence: 99%

LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging

2017

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Abstract:The LinoSPAD camera system is a modular, compact and versatile time-resolved camera system, combining a linear 256 high fill factor pixel CMOS SPAD (single-photon avalanche diode) sensor with an FPGA (field-programmable gate array) and USB 3.0 transceiver board. This modularization permits the separate optimization or exchange of either the sensor front-end or the processing back-end, depending on the intended application, thus removing the traditional compromise between optimal SPAD technology on the one hand and time-stamping technology on the other hand. The FPGA firmware implements an array of 64 TDCs (time-to-digital converters) with histogram accumulators and a correction module to reduce non-linearities. Each TDC is capable of processing over 80 million photon detections per second and has an average timing resolution better than 50 ps. This article presents a complete and detailed characterization, covering all aspects of the system, from the SPAD array light sensitivity and noise to TDC linearity, from hardware/firmware/software co-design to signal processing, e.g., non-linearity correction, from power consumption to performance non-uniformity.

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Thermometer-to-binary encoder with bubble error correction (BEC) circuit for Flash Analog-to-Digital Converter (FADC)

Cited by 17 publications

References 13 publications

Adiabatic technique for fat tree decoder to be used in flash ADCs

Adiabatic technique for fat tree decoder to be used in flash ADCs

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging

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