Thermosonic Flip Chip Interconnection Using Electroplated Copper Column Arrays

Gao, Shan; Holmes, Andrew S.

doi:10.1109/tadvp.2006.884812

Cited by 18 publications

(3 citation statements)

References 24 publications

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“…TS bonding was carried out using a custom bonder developed for thermosonic flip chip assembly [17]. Each PZT pad was bonded to the centre of a gold-metallised silicon die.…”

Section: Thermosonic Bondingmentioning

confidence: 99%

Laser transfer of sol–gel ferroelectric thin films using an ITO release layer

Bansal

Hergert

Dou

et al. 2011

Microelectronic Engineering

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A new laser transfer process is reported which allows damage-free transfer of ferroelectric thin films from a growth substrate directly to a target substrate. The thin film ferroelectric material is deposited on a fused silica growth substrate with a sacrificial release layer of ITO (indium tin oxide). Regions of the film that are to be transferred are then selectively metallised, and bonded to the target substrate. Separation from the growth substrate is achieved by laser ablation of the ITO release layer by a single pulse from a KrF excimer laser, with the laser light being incident through the growth substrate. The residual ITO on the transferred ferroelectric layer is electrically conducting, and may be suitable for incorporation into the final device, depending on the application. The new process has been demonstrated for 500 nm-thick layers of sol-gel PZT which were thermosonically bonded to a silicon target substrate prior to laser release. The transferred films show ferroelectric behaviour and have a slightly reduced permittivity compared to the as-deposited material.

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“…TS bonding was carried out using a custom bonder developed for thermosonic flip chip assembly [17]. Each PZT pad was bonded to the centre of a gold-metallised silicon die.…”

Section: Thermosonic Bondingmentioning

confidence: 99%

Laser transfer of sol–gel ferroelectric thin films using an ITO release layer

Bansal

Hergert

Dou

et al. 2011

Microelectronic Engineering

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“…While the size of electronic devices continues to decrease and the number of I/Os per chip keeps increasing, the size and pitch of solder bumps need to be as small as possible, which gives rise to great concerns over their reliability. As an alternative to solder bumps, Cu-pillars have been suggested, due to their significant advantages (Tummala, 2006; Lu and Wong, 2009; Gerber et al , 2011; Ebersberger and Lee, 2008; Gao and Holmes, 2006; Liu and Liu, 2008). Most importantly, the electromigration-resistance performance of Cu pillars is much better, compared with that of solder bumps.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration

Xiao

Munief

et al. 2016

SSMT

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2016),"Thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components: a review", Soldering & Surface Mount Technology, Vol. 28 Iss 2 pp. 41-62 http://dx.If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to fabricate a new Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration. Design/methodology/approach -The Cu-Sn-Ni-Cu interconnection microstructure is fabricated by a three-mask photolithography process with different electroplating processes. This microstructure consists of pads and conductive lines as the bottom layer, Cu-Sn-Ni-Cu pillars with the diameter of 10-40 m as the middle layer and Cu conductive lines as the top layer. A lift-off process is adopted for the bottom layer. The Cu-Sn-Ni-Cu pillars are fabricated by photolithography with sequential electroplating processes. To fabricate the top layer, a sputtered Cu layer is introduced to prevent the middle-layer photoresist from being developed. With the final Cu electroplating processes, the Cu-Sn-Ni-Cu interconnection microstructure is successfully achieved. Findings -The surface morphology of Cu-Sn pillars consists of densely packed clusters which are formed by an ordered arrangement of tetragonal Sn grains. The diffusion of Cu atoms into the Sn phases is observed at the Cu/Sn interface. Furthermore, the obtained Cu-Sn-Ni-Cu pillars have a flat surface with an average roughness of 13.9 nm. In addition, the introduction of Ni layer between the Sn and the top Cu layers in the Cu-Sn-Ni-Cu pillars can mitigate the diffusion of Cu atoms into Sn phases. The process is verified by checking the electrical performance using four-point probe measurements. Originality/value -The method described in this paper which combined a three-mask photolithography process with sequential Cu, Sn, Ni and Cu electroplating processes provides a new way to fabricate the interconnection microstructure for future electromigration studies.

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“…There have been several reports related to gold-gold thermocompression or thermosonic bonding as a potential solder-free solution. [12][13][14] Unfortunately, the cost of gold and the creation of metallurgical joints ͑i.e., not an all-copper interconnect structure͒ are potentially problematic.…”

mentioning

confidence: 99%

Electroless Copper Deposition with PEG Suppression for All-Copper Flip-Chip Connections

Osborn

Galiba

Kohl

2009

J. Electrochem. Soc.

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A fabrication technique using electroless copper deposition has been used to produce all-copper chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on a chip and substrate. Previously, solid copper-to-copper bonding was demonstrated using a known electroless copper bath followed by low temperature annealing at 180°C for 1 h in a nitrogen environment. Although the process feasibility was demonstrated, it was inherently slow and required excessive process time. In this paper, an acceleration-suppression approach to copper plating was used to achieve a rapid deposition of high quality copper in enclosed regions. Elevated temperature was used for acceleration along with poly͑ethylene glycol͒ ͑PEG͒ suppression. High temperature increased the transport of reactants and products in spatially restricted regions, and the addition of PEG provided control of the deposition rate. This allowed a kinetically controlled deposition while still maintaining good quality copper deposits without excessive porosity. Plating rates as high 6 m/h in the spatially restricted region between mated pillars were achieved.

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Thermosonic Flip Chip Interconnection Using Electroplated Copper Column Arrays

Cited by 18 publications

References 24 publications

Laser transfer of sol–gel ferroelectric thin films using an ITO release layer

Laser transfer of sol–gel ferroelectric thin films using an ITO release layer

Fabrication and characterization of Cu-Sn-Ni-Cu interconnection microstructure for electromigration studies in 3D integration

Electroless Copper Deposition with PEG Suppression for All-Copper Flip-Chip Connections

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