The properties of a new aqueous-base-develop, negative-tone photosensitive polynorbornene have been characterized. High-aspect-ratio features of 7:1 (height:width) were produced in 70-lm-thick films in a single coat with straight side-wall profiles and high fidelity. The polymer films studied had contrast of 12.2 and low absorption coefficient. To evaluate the polymerÕs suitability to microelectronics applications, epoxy crosslinking reactions were studied as a function of processing condition through Fourier-transform infrared spectroscopy, nanoindentation, and dielectric measurements. The fully crosslinked films had an elastic modulus of 2.9 GPa and hardness of 0.18 GPa.

A fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output connections. Electroless copper plating followed by low-temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The ability to fuse the two copper surfaces at modest temperature and pressure is demonstrated. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180°C. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars ͑pillar gap͒ as large as 65 m could be overcome, resulting in good pillar-to-pillar bonding. Successful silicon-on-silicon and silicon-on-FR-4 bonding was achieved with no degradation of the organic board.

A copper-to-copper bonding process was developed for an all-copper, chip-to-substrate interconnect technology. High aspect ratio polymer molds for electroplating were formed using a photodefinable polymer on both the chip and the substrate surfaces. Copper pillars were fabricated by electroplating metal in the polymer molds. The chip-to-substrate all-copper connections were formed by joining the two pillars with electroless copper plating followed by an anneal process. The copper-to-copper bonding of the high aspect ratio pillars does not require the use of solder or other noncopper metals. Mechanical shear force measurements were used to characterize the bonding process as a function of annealing conditions. Excellent bond strength of the electrolessly joined pillars was achieved with a 250°C anneal, with the bond strength of the copper pillar interconnects exceeding 148 MPa. High aspect ratio pillars can provide mechanical compliance, and the electroless fabrication method compensates for pillar misalignment and nonplanarity of the bonded surfaces.

A fabrication technique using electroless copper deposition has been used to produce all-copper chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on a chip and substrate. Previously, solid copper-to-copper bonding was demonstrated using a known electroless copper bath followed by low temperature annealing at 180°C for 1 h in a nitrogen environment. Although the process feasibility was demonstrated, it was inherently slow and required excessive process time. In this paper, an acceleration-suppression approach to copper plating was used to achieve a rapid deposition of high quality copper in enclosed regions. Elevated temperature was used for acceleration along with poly͑ethylene glycol͒ ͑PEG͒ suppression. High temperature increased the transport of reactants and products in spatially restricted regions, and the addition of PEG provided control of the deposition rate. This allowed a kinetically controlled deposition while still maintaining good quality copper deposits without excessive porosity. Plating rates as high 6 m/h in the spatially restricted region between mated pillars were achieved.

A fabrication technique involving electro-and electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at 180°C. The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate interconnects is modeled in this paper. The elastic, thermomechanical behavior and electrical performance of the chip-to-substrate interconnects are related to the geometric parameters of the pillars ͑pitch, diameter, and aspect ratio͒ and physical properties of the interconnects ͑yield stress, coefficient of thermal expansion, Young's modulus, Poisson's ratio, and electrical conductivity͒. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48-100 m and height of 508-657 m are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38-100 m diameter and height from 441 to 617 m.