Low-Temperature Bonding of Copper Pillars for All-Copper Chip-to-Substrate Interconnections

He, Ate; Osborn, Tyler; Allen, Sue Ann Bidstrup; Kohl, Paul A.

doi:10.1149/1.2353905

Cited by 43 publications

(23 citation statements)

References 5 publications

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“…The bond strength has been shown to be retained when annealing blanket BCB-BCB bonds at temperatures up to 400 o C [10], in contrast to the thermal degradation of BCB at 400 o C as previously reported [22].. The mechanism for formation of voids at the Cu-Ta-BCB interface is expected to follow two steps: 1) line edge trenching during CMP creates small facets at the edges of features, and 2) these facets grow due to grain reorientation of the copper during bonding and/or annealing at temperatures above 250 o C. A possible mitigation strategy could include lower temperature copper bond formation, an area of current research [23][24].…”

Section: Discussionmentioning

confidence: 68%

Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

McMahon

Chan

Lee

et al. 2008

2008 58th Electronic Components and Technology Conference

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This paper examines the bonding interfaces in a back-endof-line (BEOL) compatible wafer-level three-dimensional (3D) integrated circuit (IC) technology platform with wafer bonding of damascene patterned metal/adhesive surfaces. Copper and partially cured benzocyclobutene (BCB) are selected as the metal and adhesive, respectively. To prevent bonding voids and defects, the Cu-Ta-BCB, Cu-Cu, and BCB-BCB interfaces are investigated. Bonding voids and defects at the Cu-Ta-BCB and Cu-Cu interfaces are attributed to surface defects, topography, and thermomechanical stress resulting in plastic deformation of the copper during bonding. Defects observed at the BCB-BCB interface are attributed to an inability to accommodate large post-CMP topography. Short-loop wafer bonding experiments are performed using a process that eliminates the Cu/Ta interconnect structure, but provides the capability to produce controlled topography. Key parameters to prevent void formation at the BCB-BCB interface are the topography depth and pitch, as well as the BCB cure, denoted here as the crosslinking percentage. For BCB-BCB bonds formed with a partial-cure preparation of ~70-90% crosslinking, features ~1 µm in pitch are accommodated when the depth of the BCB topography is less than 12 nm. The accommodation depth is increased by a factor of ~4 with 50% crosslinked BCB. IntroductionThe 3D integration technology platform with wafer bonding of damascene patterned metal/adhesive redistribution layers [1,2] would provide the capability for high-density inter-wafer interconnect and could produce well-bonded BCB-BCB and Cu-Cu interfaces in one unit process step. After a single-level damascene patterned Cu/BCB layer is added to fully fabricated IC wafers, the patterned surfaces are forced together at elevated temperature to promote bonding of the BCB-BCB and Cu-Cu interfaces. This 3D platform enables heterogeneous integration with a high density of low inductance inter-wafer interconnects.After bonding, a typical process flow employs top-side wafer thinning to a stop layer. Stop layer approaches include chemically inert layers such as buried oxide (BOX) in silicon on insulator (SOI), or patterned layers such as via-first isolated trenches. If a chemical etch stop is utilized, then through-silicon via (TSV) formation follows thinning. In either stop layer approach, the density of interconnect at the top of the stack will be limited by the TSV density, which is expected to be lower than that of the bonded Cu-Cu interwafer interconnect.The process can be repeated to allow addition of more functional layers to the top of the stack after TSV processing. Such addition is possible using a number of approaches, but

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Section: Discussionmentioning

confidence: 68%

Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

McMahon

Chan

Lee

et al. 2008

2008 58th Electronic Components and Technology Conference

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“…In addition, the maximum shear stress is also limited by the maximum adhesion strength between the copper pillar and the substrate. [12] The average shear stress was measured to be 148 MPa, as presented in the initial report of this work. [12] Additional and more stringent criteria may also exist which further limits the maximum stress at the pillar-to-substrate, or pillar-to-chip interface, such as the mechanical strength of the interlayer dielectric on the chip or chip cracking.…”

Section: Modeling Resultsmentioning

confidence: 93%

All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability

Osborn

Lightsey

et al. 2008

2008 58th Electronic Components and Technology Conference

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A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180ºC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength.The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 µm could be overcome resulting in good pillar-topillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board.The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 µm to 100 µm and height of 508 µm to 657 µm are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 µm to 100 µm diameter and height from 441 µm to 617 µm.

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“…Uniformly fabricated copper plugs as small as 20 mm by 20 mm with an aspect ratio of 7 : 1 have been reported using this technique on 100-mm wafers. In work reported by He et al, copper bonding using electroless-plated copper was demonstrated with subsequent annealing at 250 8C for large copper plugs [92]. This process allows bonding at temperatures lower than those previously reported for evaporated copper [32][33][34][35][36]64] and sputtered copper [51].…”

Section: Through-silicon Viasmentioning

confidence: 99%

“…Research in filling of TSVs with electroplated copper for 3D applications has been accomplished by a number of groups [9,17,86,87,91,92]. As mentioned above, geometry of the via is critical for obtaining void-free copper filling, but a number of issues exist in the plating process as well: seed deposition, bottom-up filling, and bonding using electrochemically deposited copper.…”

Section: Through-silicon Viasmentioning

confidence: 99%

Three‐Dimensional (3D) Integration

McMahon

Gutmann

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Three-dimensional (3D) integration with interstrata vias has the potential of improving system performance while providing a platform for heterogeneous integration. Performance improvement in 3D integrated circuits (ICs) is mainly due to the reduction of interconnect length, which decreases interconnect delay and power consumption [1,2]. Small form factor is achieved in 3D ICs due to the stacking of active device layers one on top the other. A path for heterogeneous integration is realized if this stacking is done in a fashion that is back-end-of-line (BEOL) compatible, because interconnecting devices using fully fabricated wafers can reduce process incompatibilities.Approaches to 3D integration are often divided into die-level approaches and wafer-level approaches. Most often, the heterogeneous integration and small form factor advantages are obtained with die-level approaches; in addition, high performance and low manufacturing cost can be achieved with wafer-level approaches.CMP has permeated many aspects of IC processing but is particularly a dominant factor in BEOL interconnection. Copper damascene patterning has become the standard methodology for building a large number of interconnect layers in the vast majority of high-performance ICs. In 3D ICs, CMP is also critical in backside thinning, surface roughness reduction, and, in particular, feature topography control. Topography mitigation can particularly be a critical Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li

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Low-Temperature Bonding of Copper Pillars for All-Copper Chip-to-Substrate Interconnections

Cited by 43 publications

References 5 publications

Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability

Three‐Dimensional (3D) Integration

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