Thin-film as enabling passive integration technology for RF SoC and SIP

Abstract

As transistor dimensions scale down and CMOS and SiGe are increasingly replacing GaAs for microwave and mm-wave applications, circuit performance becomes increasingly determined by the on-chip passive component quality. However, as process technologies advance, on-chip metals and dielectrics are typically thinned to lower the achievable pitch hereby increasing the resistance and parasitic capacitance and decreasing the Q of on-chip passives. Hence, several semiconductor, MEMS and packaging technologies aim at improving Q and integration density of onchip (e.g. an add-on thick Cu/SILK module) and in-package (e.g. with deposited (MCM-D) or ceramic (MCM-C) multi-chip module technology) passives [1].IMEC's thin-film technology uses alternating layers of BCB (benzo-cyclobutene, K=2.65) and electroplated Cu (3 to 20µm thick, min. width/thickness=1) combined with TaN resistors and Ta 2 O 5 capacitors. When applied on active wafers, it is considered a wafer-level packaging (WLP) technology; when applied on an intermediate glass or high-resistivity (HR) Si substrate, it is considered a thin-film SiP technology or MCM-D. MCM-D on glass allows to realize high-Q passives and SiP modules from RF to Vband [2]. MCM-D on HR-Si, however, offers better opportunities for the realization of 3D SiP modules due to better thermal conductivity of the substrate and the possibility to integrate vias and perform wafer thinning. Thin-film WLP technology, on the other hand, is originally introduced for the realization of on-chip flipchip redistribution layers and hereby offers opportunities to integrate high-Q transmission lines and inductors on-chip.A schematic cross section of IMEC's RF thin-film WLP and MCM-D technology is shown in Fig. 21.5.1: interconnects and inductors are preferably realized in M1; M2 is used for overpasses and acts as under bump metallurgy for the solder bumps. A 16µm BCB1 layer is used which results in good RF properties for SiP and SoC passives, however, BCB-vias realized using conventional photolithography become relatively large [3] in this case. Hence, a high aspect ratio via (HARVi) is used to connect M1 to the underlying layers hereby reducing the size and the parasitic capacitance of the via. The increased BCB-1 thickness (t BCB1 ) also decreases the parasitic capacitances of on-chip bond pads which is beneficial for mm-wave applications.The measured losses, Q and dimensions of the thin-film microstrip (TFML) and coplanar waveguide (CPW) lines are shown in Fig. 21.5.2; a CPW on glass is shown as reference. Increasing t BCB1 lowers the ε eff of the line hereby reducing interconnect loss (dB/mm) and increasing Q as 50Ω lines are obtained with wider strips: the Q of the 50Ω 40µm-wide TFML tops 40 from 40 to 110GHz (note, Qs of 10 and 20 are reported at 40GHz for back-end integrated microstrip and CPW [4,5]). At mm-wave frequencies, the TFML and CPW on glass losses are comparable although a narrower line is used, indicating that TFML allows a higher interconnect density.When ε eff of the line decreases, the wavel...

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