Thin Ge buffer layer on silicon for integration of III-V on silicon

Yang, Junjie; Jurczak, P.; Fan, Cunzheng; Li, Keshuang; Tang, Mingchu; Billiald, Luke; Beanland, Richard; Sanchez, Ana M.; Liu, Huiyun

doi:10.1016/j.jcrysgro.2019.02.044

Cited by 22 publications

(21 citation statements)

References 29 publications

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“…Hayafuji et al [ 321 ] reported that the mechanism behind SLs effect is the hardening of crystal and bending of dislocation along the superlattice interface. In addition, growth of buffer layer of Ge with high epitaxial quality, [ 322 , 323 ], LT/HT epitaxy (see Figure 46 a), and CMP are popular methods to control the propagation of misfit dislocations, as shown in Figure 46 b [ 324 ].…”

Section: Iii-v Materialsmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Iii-v Materialsmentioning

confidence: 99%

“…with high epitaxial quality, [322,323], LT/HT epitaxy (see Figure 46 (a)), and CMP are popular methods to control the propagation of misfit dislocations, as shown in Figure 46 (b) [324].…”

Section: Global Epitaxymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Because the cracks were preferentially formed at the edges of the notches acting as stress concentrators, the periodic crack arrays could be achieved, resulting in a crack-free region (2 × 2 mm 2 ) where 5.8 µm-thick GaAs-based solar cell structures were grown. Recently, instead of a thick GaAs buffer layer, growing a thin Ge layer on Si was proposed [143,247]. For example, Yang et al [143] demonstrated that although a 300 nm-thick thin Ge layer replaced the conventional 1 µm-thick GaAs buffer layer for InAs/GaAs QD lasers on Si, the fabricated lasers with thin Ge buffer showed comparable performances, in terms of TDD and lasing behavior, to the conventional QD lasers with thick GaAs buffer.…”

Section: Minimizing Thermal Cracksmentioning

confidence: 99%

Heteroepitaxial Growth of III-V Semiconductors on Silicon

et al. 2020

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Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.

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“…Note that the growth conditions were identical for both samples during the growth of all subsequent layers. The laser structure is shown schematically in Figure 1, containing an optimised 300 nm Ge/Si VS [39]. The growth started with a three-step growth technique for the thin Ge layer.…”

Section: Crystal Growth and Device Fabricationmentioning

confidence: 99%

All-MBE grown InAs/GaAs quantum dot lasers with thin Ge buffer layer on Si substrates

Yang

Liu

Jurczak

et al. 2020

J. Phys. D: Appl. Phys.

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A high-performance III-V quantum-dot (QD) laser monolithically grown on Si is one of the most promising candidates for commercially viable Si-based lasers. Great efforts have been made to overcome the challenges due to the heteroepitaxial growth, including threading dislocations (TDs) and anti-phase boundaries (APBs), by growing a more than 2 µm thick III-V buffer layer. However, this relatively thick III-V buffer layer causes the formation of thermal cracks in III-V epi-layers, and hence a low yield of Si-based optoelectronic devices. In this paper, we demonstrate a usage of thin Ge buffer layer to replace the initial part of GaAs buffer layer on Si to reduce the overall thickness of the structure, while maintaining a low density of defects in III-V layers and hence the performance of the InAs/GaAs QD laser. A very high operating temperature of 130 °C has been demonstrated for an InAs/GaAs QD laser by this approach.

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Thin Ge buffer layer on silicon for integration of III-V on silicon

Cited by 22 publications

References 29 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Heteroepitaxial Growth of III-V Semiconductors on Silicon

All-MBE grown InAs/GaAs quantum dot lasers with thin Ge buffer layer on Si substrates

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