Thin germanium–carbon layers deposited directly on silicon for metal–oxide–semiconductor devices

Kelly, D. Q.; Wiedmann, I.; García-Gutiérrez, Domingo I.; José–Yacamán, Miguel; Banerjee, S.

doi:10.1088/0268-1242/22/1/s48

Cited by 8 publications

(4 citation statements)

References 7 publications

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“…SIMS profiles showed that the carbon segregates toward upper/lower portion of the films near the surface/interface regions. The layers are slightly compressed with a net relaxation of ∼78% and are typically too thin for optical applications but could prove useful for Ge channel MOSFETs . Our deposition experiments using GeH 3 CH 3 were conducted on a single-stage wafer configuration at significantly lower temperatures (360 °C), which precluded any of the side reactions that might lead to carbon contamination.…”

Section: Resultsmentioning

confidence: 99%

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

et al. 2007

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We describe the systematic epitaxial engineering of device-quality elemental structures in the Ge/Si system. By introducing small concentrations of (GeH 3 ) 2 CH 2 or GeH 3 CH 3 organometallic additives into conventional Ge 2 H 6 , we have developed several new low-temperature CVD growth strategies that permit heteroepitaxy of highly dissimilar materials and provide unprecedented control of film microstructure, morphology, composition, and tuning of optical properties. Optimized molecular mixtures of these compounds have enabled layer-by-layer growth via facile elimination of extremely stable CH 4 and H 2 byproducts, consistent with calculated chemisorption energies and surface reactivities. Collectively, our experiments indicate that the additives confer unique pseudosurfactant behavior that profoundly alters the classic Stranski-Krastanov growth mechanism of epitaxial Ge on Si surfaces. Using this approach, we have produced atomically smooth, carbon-free Ge layers directly on Si with dislocations densities less than 1 × 10 5 cm -2 (significantly less than those attainable from the best competing processes) at unprecedented low temperatures (350-420 °C) compatible with selective area growth applications. Full relaxation of the film is readily achieved via formation of Lomer dislocations confined to the Ge/Si interface, which should, in principle, allow film dimensions approaching bulk values to be achieved on a Si substrate. Here, films with thicknesses up to several micrometers have been grown for use as passive/ active heterostructure components. The practical utility of the approach is demonstrated for the first time by growing pure Ge seamlessly, conformally, and selectively in the "source/drain" regions of prototypical device structures. This innovation represents an ultimate extension of uniaxial strain techniques using group IV materials and is likely to have applications in the integration of microelectronics with optical components (photodiodes) into a single chip. As an additional example for high-mobility device template application, we have grown tensile Si films on the Ge buffers via decomposition of SiH 3 SiH 2 SiH 3 . The new Ge growth processes also provide a unique route to extend the utility of elemental Ge into the wider IR optoelectronic domain by tuning its fundamental optical properties using tensile strain as a main parameter. In this study, we use the metal-organic additives to circumvent traditional surface-energy limitations and produce for the first time high-quality, thermally stable, tensile strained Ge layers at low temperature (350-380 °C) on Ge 1-y Sn y -buffered Si(100). The precise strain state of the epilayers is controlled by varying the Sn content of the buffer, yielding tunable record-high tensile strains as high as 0.43%. This strain-tuning strategy may offer the prospect of producing direct optical gaps in elemental Ge.

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Section: Resultsmentioning

confidence: 99%

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

et al. 2007

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“…Because of the low solid solubility of C in Ge, C tends to segregate toward the interface of Ge 1−x C x /Si substrate and thus limits the defects near the bottom interface. As a result, the upper portion of the Ge 1−x C x layer has a much lower defect density than that of pure Ge grown directly on Si (1 0 0) [7,8]. On the other hand, the in situ Si capping of the Ge 1−x C x layer prevents GeO x formation and passivates the Ge 1−x C x surface.…”

Section: Introductionmentioning

confidence: 99%

Effects of Si-cap thickness and temperature on device performance of Si/Ge_1−xC_x/Si p-MOSFETs

Jamil¹,

Liu²,

Ferdousi³

et al. 2010

Semicond. Sci. Technol.

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This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge 1−x C x /Si p-MOSFETs. The silicon-cap thickness (3-9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and I on -I off ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge 1−x C x interface was quantitatively extracted by fitting the stair-case behavior of split C-V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.

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“…Figure 4b shows a high magnification XTEM of the Ge 1-x C x layer with a Si cap. A etch pit density (EPD) formula modified to work with thin films determine a defect density of 3.0 ×10 5 cm -2 , while the a Ge layer of similar thickness grown over an entire 4" wafer had a defect density of 2.8 ×10 8 cm -2 , and no defects were found on the bulk Ge wafer (23). AFM analysis of the surface shows very low RMS roughness of 3Å, which is among the lowest ever reported for Ge films on Si.…”

Section: Germanium-carbon Directly On Silicon Pmosfetsmentioning

confidence: 99%

Enhanced Channel Mobility Materials for MOSFETs on Si Substrates

et al. 2007

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MOS high-k/metal devices with Ge and GaAs semiconductors were used to fabricate PMOS and NMOS devices, respectively. Selective epitaxially grown (SEG) Ge PMOSFETs with a 2× enhanced IDsat and greater than 2× improvement in hole mobility compared to Si PMOSFETs. Buried-channel (BC) Ge1-xCx PMOSFETs showed a 2× enhancement in IDsat over Si control PMOSFET and ~1.5× improvement in effective mobility over universal curve for Si. The corresponding enhancement for surface channel (SC) Ge1-xCx PMOSFETs was 3× and ~2.5×, respectively. The Ion/Ioff ratio for (BC) Ge1-xCx was greater than 5×104. GaAs NMOS capacitors using two different chemical surface treatments NH4OH and (NH4)2S prior to ALD-Al2O3 deposition were examined. Both treatments remove As2O3/As2O6 upon Al2O3 deposition and unpinned the Al2O3/GaAs interface. However (NH4)2S has better frequency dispersion behavior and slightly smaller capacitance equivalent thickness (CET) than NH4OH treatment. Quasi-static CV measurement confirmed formation of a true inversion layer in GaAs.

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Thin germanium–carbon layers deposited directly on silicon for metal–oxide–semiconductor devices

Cited by 8 publications

References 7 publications

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

Effects of Si-cap thickness and temperature on device performance of Si/Ge_1−xC_x/Si p-MOSFETs

Enhanced Channel Mobility Materials for MOSFETs on Si Substrates

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Thin germanium–carbon layers deposited directly on silicon for metal–oxide–semiconductor devices

Cited by 8 publications

References 7 publications

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

Epitaxy-Driven Synthesis of Elemental Ge/Si Strain-Engineered Materials and Device Structures via Designer Molecular Chemistry

Effects of Si-cap thickness and temperature on device performance of Si/Ge1−xCx/Si p-MOSFETs

Enhanced Channel Mobility Materials for MOSFETs on Si Substrates

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Effects of Si-cap thickness and temperature on device performance of Si/Ge_1−xC_x/Si p-MOSFETs