Thin-oxide damage from gate charging during plasma processing

Fang, Sychyi; McVittie, J.P.

doi:10.1109/55.145056

Cited by 138 publications

(34 citation statements)

References 10 publications

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“…IC design rules include considerations to mitigate damage to gate oxides by antenna effects (charging during plasmabased processing) [67], [68]. Post-processing steps that employ plasma can cause similar damage, which can be avoided by depositing a metal layer beforehand to electrically short all the exposed CMOS connections.…”

Section: Damage To Circuits During Post-processingmentioning

confidence: 99%

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Datta-Chaudhuri

Smela

Abshire

2016

IEEE Trans. Biomed. Circuits Syst.

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Abstract-CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.Index Terms-Biosensor, heterogeneous integration, lab-on-achip, lab-on-CMOS, microfluidics, system on a chip.

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Section: Damage To Circuits During Post-processingmentioning

confidence: 99%

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Datta-Chaudhuri

Smela

Abshire

2016

IEEE Trans. Biomed. Circuits Syst.

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“…In addition, A/V , and MV/cm are known constants [30]. Note that (10) assumes that the current density is uniform across the gate oxide area of the test structure. Using the largest potential difference (4.1 V) shown in profile A of Fig.…”

Section: E Whole-wafer Maps Of Plasma-induced Damagementioning

confidence: 99%

“…This damage is the result of exposure to the various particle and energy fluxes present in the plasma environment and for gate oxides can be caused by wafer surface charging, [7]- [9]. The damage generated by this charging is the result of Fowler-Nordheim (F-N) current stressing of thin oxides under floating gates, [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

Friedmann

Shohet

Mau

et al. 1997

IEEE Trans. Semicond. Manufact.

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Abstract-In this work, the effects of plasma-parameter variations on charging damage to polysilicon-gate MOS capacitor test structures exposed to O 2 electron-cyclotron-resonance (ECR) plasmas are investigated. Results will show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities.

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“…To passivate the interface states at the Si-SiO 2 interface the role of hydrogen became even more prominent. The other major source of plasma damage in MOS structures was the current stress to the oxide during plasma processing or the so-called antenna effect (9). This effect severely impacted the device performance especially the hot carrier lifetime degradation depending on polarity of current stress during plasma damage (10).…”

Section: Introductionmentioning

confidence: 99%

(Electronics & Photonics Division Award Presentation) Si-SiO₂ Interface to High-K-Ge/III-V Interface: Passivation and Reliability

Misra

2013

ECS Trans.

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The Si-SiO2 interface is one of the most important semiconductor-dielectric interfaces that has been studied extensively over many decades. The understanding and control of structural and electronic properties of Si-SiO2 interfaces has provided many clues for technological advancement. The article discusses how the Si-SiO2 interface migrated through the technological landscape like plasma processing damage, hot carrier effects and negative bias temperature instability (NBTI) and subsequent passivation techniques using hydrogen to nitrogen. Introduction of high-k gate dielectrics brought significant attention to the interface between silicon and high-k dielectrics but Si-SiO2 interface continued to be important because of the presence of a SiO2-based interfacial layer. With deposition of high-k gate dielectrics high carrier mobility substrates (Ge/III-V) are currently being considered as the channel materials. To obtain a high quality interface between the high-k dielectrics and the high mobility substrates some issues like deposition process, precise selection of deposition parameters, predeposition surface treatments, appropriate passivation techniques and subsequent annealing temperatures are also outlined.

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Thin-oxide damage from gate charging during plasma processing

Cited by 138 publications

References 10 publications

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

(Electronics & Photonics Division Award Presentation) Si-SiO₂ Interface to High-K-Ge/III-V Interface: Passivation and Reliability

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Thin-oxide damage from gate charging during plasma processing

Cited by 138 publications

References 10 publications

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Plasma-parameter dependence of thin-oxide damage from wafer charging during electron-cyclotron-resonance plasma processing

(Electronics & Photonics Division Award Presentation) Si-SiO2 Interface to High-K-Ge/III-V Interface: Passivation and Reliability

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(Electronics & Photonics Division Award Presentation) Si-SiO₂ Interface to High-K-Ge/III-V Interface: Passivation and Reliability