Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2013
DOI: 10.1109/ipfa.2013.6599153
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Thin silicon wafer processing and strength characterization

Abstract: Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three-dimensional integrated circuits (3D-IC). The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these… Show more

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Cited by 15 publications
(1 citation statement)
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“…In comparison, the plasma etched wafer surface is smoother than the chemical etched wafer surface [105]. The silicon surface condition after the wafer grinding process is one of the most critical factors, which affects the silicon die strength [107]. The silicon dies with smooth surface always show higher strength than those silicon dies with rough surfaces [104,108].…”
Section: Effect Factors On Silicon Die Strengthmentioning
confidence: 99%
“…In comparison, the plasma etched wafer surface is smoother than the chemical etched wafer surface [105]. The silicon surface condition after the wafer grinding process is one of the most critical factors, which affects the silicon die strength [107]. The silicon dies with smooth surface always show higher strength than those silicon dies with rough surfaces [104,108].…”
Section: Effect Factors On Silicon Die Strengthmentioning
confidence: 99%