Three-Dimensional Capacitor Embedded in Fully Cu-Filled Through-Silicon Via and Its Thermo-Mechanical Reliability for Power Delivery Applications

Abstract

embedded in fully Cu-filled through-silicon via and its thermo-mechanical reliability for power delivery applications. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 393-398.

Surface Smoothing by Atomic Layer Deposition and Etching for the Fabrication of Nanodevices

“…With the semiconductor industry pursuing ever improved device performance and yield, the quality of surfaces and interfaces plays an increasingly large role, with nanoscale surface roughness often being a limiting parameter in final device performance. Roughness at interfaces can act as a nucleation point for defects, introduce nonuniformities, and contribute to trap states. − For example, in both FinFETs and gate-all-around FETs, roughness leads to variability of the threshold voltage due to deviating gate lengths, while roughness in the fins/nanowires reduces the carrier mobility. ,− Metal–insulator–metal (MIM) capacitor structures in radiofrequency and analog applications are detrimentally affected by roughness, causing nonuniform electric fields and consequently an increased leakage current and electronic noise. ,, In the field of photonics, sidewall roughness in optical waveguides has been shown to cause scattering losses. , This is just a small selection of applications where controlling surface roughness is vital to improve final device performance.…”

“… 1 , 5 − 7 Metal–insulator–metal (MIM) capacitor structures in radiofrequency and analog applications are detrimentally affected by roughness, causing nonuniform electric fields 10 and consequently an increased leakage current and electronic noise. 3 , 8 , 9 In the field of photonics, sidewall roughness in optical waveguides has been shown to cause scattering losses. 11 , 12 This is just a small selection of applications where controlling surface roughness is vital to improve final device performance.…”

Analysis and evaluation of noise coupling between through-silicon-vias

“…Through-silicon-vias (TSVs), the biggest feature of 3D-SICs, enable vertical signal transfer among stacked ICs which enhances performance and energy by optimized signal lines between stacked ICs [8][9][10][11][12][13]. Although wider signal bus is required for enormous scale data transfer, densely manufactured signal bus needs to solve crosstalk among the channels [14][15][16][17][18][19][20] as well as power line noise [21][22][23][24][25][26][27]. To avoid bit error caused by such crosstalk, it requires frequency or voltage optimization that cause additional issues like lower data transfer speed or larger power consumption, respectively [28,29].…”