No abstract

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

This study presents the design and development of surface electrode ion traps on glass and Si substrate, as well as their RF characterizations and performance benchmarking. In this case, ion-trap on-glass shows superior performances in all necessary criteria. In terms of RF characterizations, ion-traps on glass have Q factor of greater than 900. This is significantly higher than the Q factor of its silicon counterparts, which are around 20 -300. Such a high Q factor results in power spectral density (PSD) of greater than 10W/MHz. On the other hand, iontraps on-silicon produce PSD values of lower than 3W/MHz. In terms of RF performance, ion-trap on-glass shows insertion loss lower than 0.2 dB at 60MHz. This is more superior to insertion loss values of ion-traps on-silicon, which are around 1 -4 dB. The ion-traps metallization is developed using three metallization layers (0.1µm Ti barrier layer, 2.5 -3.7µm Cu, and 0.3µm Au) on top of dielectric. The on-chip resonance condition can be maintained upon the packaging integration. The laser optical setup for ion-trapping is verified to capture single 88 Sr + ion.

Surface electrode ion trap is one of the key devices in modern ion trapping apparatus to host the ion qubits to perform quantum computation. Surface traps fabricated on silicon substrate have the versatility for complex electrode fabrication with 3D integration capability. However, Si induced dielectric loss needs to considered for trap design and the additional ground structure is necessarily incorporated into the surface electrodes fabrication. In this work, surface electrode ion trap is fabricated using standard Cu back end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: (1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes, (2) the use of dry etching to form the fine gap oxide trench between the electrodes for reducing the charge induced stray electric field, (3) the use of Cu mesh ground structure to enhance the resonance performance of the trap, and (4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties is obtained from the fabricated ion trap, with leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with RF line widths of 80 and 40 μm are evaluated for their resonance performances without and with ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with output power increment of 11 and 13 dBm and Q factor increment of 2 and 6, for the corresponding trap types.

In this study, the authors present a novel concept for the design of single‐pole multiple‐throw (SPMT) switches using defected ground structure low‐pass filter (DGS LPF). The DGS LPF produces enhanced inductance to compensate the parasitic capacitance of the control transistors. As a result, the SPMT switch will consume much less silicon area. The concept is experimentally validated with a single‐pole double‐throw (SPDT) switch and a single‐pole four‐throw (SP4T) switch in 65‐nm CMOS. The active area of the SPDT and SP4T switches are less than 130 × 150 μm2 and 180 × 165 μm2, respectively.