Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

Dang, Bing; Shapiro, M. J.; Andry, Paul; Tsang, C. K.; Sprogis, E.; Wright, S. L.; Interrante, M. J.; Griffith, J.; Truong, Viet Giang; Guerin, Luc; Liptak, R. W.; Berger, D.; Knickerbocker, John

doi:10.1109/led.2010.2084068

Cited by 23 publications

(3 citation statements)

References 5 publications

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“…For example, trench capacitors make good use of the depth of substrate and achieve extremely high capacitance density [14], [15]. On top of that, 2.5D/3D heterogenous integration enables processing of capacitors in a separated die so that they do not have to compete with transistors for surface areas [16]- [19]. Nevertheless, with all available current technologies, the size of capacitors is still a few times greater than that of the logic circuits in many capacitance-hungry applications, e.g., integrated voltage regulators (IVRs) [20].…”

Section: Introductionmentioning

confidence: 99%

Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via

Lin

Tan

2018

IEEE Trans. Compon., Packag. Manufact. Technol.

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A new approach to implement integrated capacitors with superb capacitance density, called "three-dimensional (3D) embedded capacitor" is investigated. It is realized by embedding metal-insulator-metal (MIM) layers onto the trenches of throughsilicon-vias (TSVs) prior to copper filling. An ultrahigh capacitance density of 5,621.8 nF/mm 2 was envisioned according to our model, which is ~13× of 440.0 nF/mm 2 from a conventional trench capacitor with the same design parameters. A set of prototypes were fabricated and characterized for assessment of structure integrity and electrical performance of the 3D embedded capacitors. Scanning electron microscope (SEM), transmission electron microscope (TEM) and energy-dispersive X-ray spectroscopy (EDX) analysis results show good step coverage and stoichiometry of the MIM layers deposited. The capacitance density of up to 3,856.4 nF/mm 2 was achieved for the prototypes with MIM layers formed by atomic layer deposition (ALD). A leakage current density as low as 1.61×10 -7 A/cm 2 at 4.3V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3,776.6 nF/mm 2 .

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Section: Introductionmentioning

confidence: 99%

Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via

Lin

Tan

2018

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…To provide effective decoupling above several hundreds of MHz, the total capacitance of the on-chip capacitors must be increased without increasing the chip area. Capacitors suitable for implementing such a decoupling solution on chips are metal oxide semiconductor (MOS) capacitors, metal-insulator-metal (MIM) capacitors, and deep trench (DT) capacitors [1][2][3]. MOS capacitors have been the most popular choice for the decoupling solution.…”

Section: Decoupling Capacitor Schemesmentioning

confidence: 99%

“…DT capacitors that are realized on silicon chips as MOS decoupling capacitors offer better capacitance density, while the leakage current is much lower compared to MOS decoupling capacitors. However, a DT capacitor typically has a thicker dielectric and occupies a much lower footprint on the silicon [1,4].…”

Section: Deep Trench Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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Exploring the benefits, challenges, and feasibility of integrating power electronics into c-Si solar cells

Nijen

Manganiello²,

Zeman³

et al. 2022

Cell Reports Physical Science

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Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

Cited by 23 publications

References 5 publications

Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via

Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via

TSV Decoupling Schemes

Exploring the benefits, challenges, and feasibility of integrating power electronics into c-Si solar cells

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