Patterning imperfections in semiconductor device fabrication may either be noncritical [e.g., line edge roughness (LER)] or critical, such as defects that impact manufacturing yield. As the sizes of the pitches and linewidths decrease in lithography, detection of the optical scattering from killer defects may be obscured by the scattering from other variations, called wafer noise. Understanding and separating these optical signals are critical to reduce false positives and overlooked defects. The effects of wafer noise on defect detection are assessed using volumetric processing on both measurements and simulations with the SEMATECH 9-nm gate intentional defect array. Increases in LER in simulation lead to decreases in signal-to-noise ratios due to wafer noise. Measurement procedures illustrate the potential uses in manufacturing while illustrating challenges to be overcome for full implementation. Highly geometry-dependent, the ratio of wafer noise to defect signal should continue to be evaluated for new process architectures and production nodes. Barnes et al.: Effects of wafer noise on the detection of 20-nm defects using optical volumetric inspection Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/08/2015 Terms of Use: http://spiedl.org/terms Barnes et al.: Effects of wafer noise on the detection of 20-nm defects using optical volumetric inspection Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/08/2015 Terms of Use: http://spiedl.org/terms Barnes et al.: Effects of wafer noise on the detection of 20-nm defects using optical volumetric inspection Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/08/2015 Terms of Use: http://spiedl.org/terms