Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias

Kirihata, T.; Golz, John; Wordeman, M.R.; Batra, Pooja; Maier, Gary; Robson, N.; Graves-Abe, Troy; Berger, Daniel; Iyer, Subramanian S.

doi:10.1109/jetcas.2016.2547738

Cited by 16 publications

(10 citation statements)

References 27 publications

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“…However, no discussion is made on leveraging vault-level parallelism and bank interleaving of HMC, since the main problem targeted by the work is implementing a fast packet matching circuit in FPGA. There is a study that utilizes 3D-stacked DRAM devices including HMC as the main memory of a system [34]. The work mainly details the production process of 3D-stacked DRAM devices, and there is no discussion on evaluating system performance.…”

Section: Related Workmentioning

confidence: 99%

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Korikawa

Kawabata

et al. 2019

IEEE Access

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New network services such as the Internet of Things and edge computing are accelerating the increase in traffic volume, the number of connected devices, and the diversity of communication. Next generation carrier network infrastructure should be much more scalable and adaptive to rapid increase and divergence in network demand with much lower cost. A more virtualization-aware, flexible and inexpensive system based on general-purpose hardware is necessary to transform the traditional carrier network into a more adaptive, next generation network. In this paper, we propose an architecture for carrierscale packet processing that is based on interleaved 3 dimensional (3D)-stacked dynamic random access memory (DRAM) devices. The proposed architecture enhances memory access concurrency by leveraging vault-level parallelism and bank interleaving of 3D-stacked DRAM. The proposed architecture uses the hash-function-based distribution of memory requests to each set of vault and bank; a significant portion of the full carrier-scale tables. We introduce an analytical model of the proposed architecture for two traffic patterns; one with random memory request arrivals and one with bursty arrivals. By using the model, we calculate the performance of a typical Internet protocol routing application as a benchmark of carrier-scale packet processing wherein main memory accesses are inevitable. The evaluation shows that the proposed architecture achieves around 80 Gbps for carrier-scale packet processing involving both random and bursty request arrivals.

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Section: Related Workmentioning

confidence: 99%

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Korikawa

Kawabata

et al. 2019

IEEE Access

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“…Attempts of direct 3D fabrication can be dated back to 1980s, mainly by exploiting the micromachining technologies. Recent progress in this area focused on the development of 3D transistor technologies, heterogeneous integration schemes of 3D circuits, and 3D printing technologies . The layout of stereoscopic field effect transistors, such as the widely adopted fin field‐effect transistors (Fin‐FETs) (tri‐gate) structures, can greatly reduce the leakage current, and shorten the gate length of the transistors.…”

Section: Introductionmentioning

confidence: 99%

Micro/Nanoscale 3D Assembly by Rolling, Folding, Curving, and Buckling Approaches

Zhang

2019

Advanced Materials

102

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The miniaturization of electronics has been an important topic of study for several decades. The established roadmaps following Moore's Law have encountered bottlenecks in recent years, as planar processing techniques are already close to their physical limits. To bypass some of the intrinsic challenges of planar technologies, more and more efforts have been devoted to the development of 3D electronics, through either direct 3D fabrication or indirect 3D assembly. Recent research efforts into direct 3D fabrication have focused on the development of 3D transistor technologies and 3D heterogeneous integration schemes, but these technologies are typically constrained by the accessible range of sophisticated 3D geometries and the complexity of the fabrication processes. As an alternative route, 3D assembly methods make full use of mature planar technologies to form predefined 2D precursor structures in the desired materials and sizes, which are then transformed into targeted 3D mesostructures by mechanical deformation. The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.

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“…With the assistance of through-silicon-via (TSV) technology [23][24][25] that enable a vertical interconnection completely through a silicon wafer, 3D IC/Si integration technologies were developed to achieve a higher level of integration than are possible with Moore technologies. Compared with 3D IC packaging, 3D IC integration can stack much thinner IC chips with TSVs and microbumps 26 (Fig. 1f), thereby offering higher integration, a smaller footprint, higher performance, and lower power consumption.…”

mentioning

confidence: 99%

“…(Copyright © 2008 & 2014 IEEE). e-g Three types of 3D integration technology and images of some representative examples: e stacked-die with wire bonding and package-onpackage stacking 22 , f memory stacking with TSVs 26 , g wafer-to-wafer bonding (bumpless) 27 . e-g are adapted with permission from refs.…”

mentioning

confidence: 99%

“…e-g are adapted with permission from refs. 22,26,27 Figure 2a shows a schematic illustration of the residual stress method used to fabricate tubular or helical 3D electronic devices at the nanoscale 1 . By controlling the relevant fabrication parameters (e.g., deposition rate, temperature, or composition), the misfit strain between the top and bottom layers induces the self-rolling of 2D precursors into deterministic 3D structures after the selective etching of the sacrificial layer 32 .…”

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confidence: 99%

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Manufacturing of 3D multifunctional microelectronic devices: challenges and opportunities

2019

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Sophisticated three-dimensional (3D) forms are expected to be one of the significant development trends in nextgeneration microelectronics because of their capabilities of rendering substantially enhanced performances, a high degree of integration, and novel functionalities. To date, a diversity of manufacturing methods has been developed for 3D microelectronic devices with different structural and functional features. Most of these methods fall into two categories, i.e., micromanufacturing technologies and mechanically guided 3D assembly approaches. From this perspective, we review the different manufacturing methods and their specific features as well as their limitations. At present, there is still no universal method that can deterministically form 3D microelectronic devices with very high geometric complexity and nanoscale precision. We offer an outlook on future developments in the manufacturing of 3D multifunctional microelectronics devices and provide some perspectives on the remaining challenges as well as possible solutions. Mechanically guided 3D assembly based on compressive buckling is proposed as a versatile platform that can be merged with micromanufacturing technologies and/or other assembly methods to provide access to microelectronic devices with more types of integrated functions and highly increased densities of functional components.

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Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias

Cited by 16 publications

References 27 publications

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis

Micro/Nanoscale 3D Assembly by Rolling, Folding, Curving, and Buckling Approaches

Manufacturing of 3D multifunctional microelectronic devices: challenges and opportunities

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