Three Dimensional integration - Considerations for memory applications

Iyer, Subramanian S.; Kirihata, T.; Barth, J.

doi:10.1109/cicc.2011.6055356

Cited by 6 publications

(1 citation statement)

References 8 publications

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“…To achieve 3D integration, heterogeneous and monolithic approaches can be pursued. The heterogeneous integration has been developed to stack several chips coming from different technology platforms and to connect them using wafer bonding and through-silicon-vias (TSVs) [3]. More recently, a 3D monolithic integration technology has been proposed by the CEA Leti [4].…”

Section: Introductionmentioning

confidence: 99%

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

Drouin

Droulers

Labalette

et al. 2017

Journal of Nanomaterials

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We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300°C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.

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Section: Introductionmentioning

confidence: 99%

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

Drouin

Droulers

Labalette

et al. 2017

Journal of Nanomaterials

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Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

Secker

Wilson

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This paper presents a double-sided flip-chip package. The package consists of a memory controller on one side of an organic substrate, and 3D-stacked, disaggregated memory chips, integrated with TSVs, on the opposite side. Thermal isolation is one of the key motivations for this configuration. Co-design of all physical layers is required to optimize the integrated 3D package within electrical and manufacturing constraints. Double-sided flip-chip packaging also presents unique challenges in the design of the power delivery network (PDN). A pre-layout design strategy is described, which optimizes the PDN design across 11 power domains to meet stringent impedance targets.

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80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Jayaraman

Leu

Viraraghavan

et al. 2018

IEEE J. Solid-State Circuits

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Three Dimensional integration - Considerations for memory applications

Abstract: This paper reviews the technology and design considerations for the implementation of 3 Dimensional integration of memory in a high performance logic environment

Cited by 6 publications

References 8 publications

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

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