Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps

Yu, Aibing; Lau, John H.; Ho, Soon Wee; Kumar, Aditya; Yin, Hnin Wai; Ching, Jong Ming; Kripesh, V.; Pinjala, D.; Chen, Scott; Chan, Chien-Feng; Chao, Chun-Chieh; Chiu, Chi-Hsin; Huang, Chi Yen; Chen, Carl

doi:10.1109/ectc.2009.5074039

Cited by 46 publications

(16 citation statements)

References 9 publications

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“…Three-dimensional (3D) integration, which refers to the system integration technology that stacks and interconnects multilayer chips vertically, has now been generally considered as the most promising solution to this predicament. Combination of high aspect ratio through silicon vias (TSVs) and ultrafine pitch microbumps presents the shortest signal transmission channels between chips, making it the mainstream scheme of 3D integration [3][4][5]. Microbumps free from defects are of crucial concerns for high quality interconnects, since they are bridges between multiple chips [6].…”

Section: Introductionmentioning

confidence: 99%

Using SOM neural network for X-ray inspection of missing-bump defects in three-dimensional integration

Liao

Chen

et al. 2015

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Using SOM neural network for X-ray inspection of missing-bump defects in three-dimensional integration

Liao

Chen

et al. 2015

Microelectronics Reliability

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“…Interconnections with high I/Os and fine pitch were needed in other to achieve the requirement of multi-function for next generation electronics [1][2][3][4][5][6]. Among the interconnection technologies, throughsilicon-via (TSV) provides especially the shortest length and the highest density which lead to significantly reduced signal delay and power consumption [7].…”

Section: Introductionmentioning

confidence: 99%

Structure effects on the electrical reliability of fine-pitch Cu micro-bumps for 3D integration

Lee

Kim

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Recently, flip chip solder bumps have been replaced by the fine-pitch solder micro-bump due to the miniaturization of electronic devices and the high performance requirement, and so on. Because of the fast decreasing size of the micro-bump and increasing power consumption needs in logic through-Si via applications, the significance of electromigration among major reliability issues have been increased. There are several important electrical current-induced reliability issues such as current crowding, polarity effect and thermomigration. And the excessive intermetallic compound (IMC) growth and Kirkendall voiding or micro voiding in micro-bump can degrade the mechanical reliability as well as electrical reliability. Therefore, the understanding of fundamental IMC growth mechanism is essential. This study systematically investigated the effects of bump structures such as solder height and UBM structure on the IMC growth kinetics and electromigration performance of Cu micro-bump. Quantitative analyses on the IMC growth kinetics during in-situ electromigration test were performed in a scanning electron microscope chamber under current stressing conditions with current density of 1.5 x 10 5 A/cm 2 at 150℃. Under high temperature and electric current stressing, the IMCs growth is accelerated by electron wind force. And the IMC phase transition time became shorter because IMC growth rates increased. In Cu/Sn-Ag and Cu/Ni/Sn-Ag system, the effect of current crowding and Joule heating was negligible in fully IMC-transformed micro-bump. Finally, microvoid formation mechanisms during IMC growth in the Cu/Ni/thin Sn system were discussed in detail.

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“…3D packaging using micro bumps and Through Silicon Vias (TSV) is emerging packaging technology to overcome the shortcoming. [2,3] Chip-to-chip stacking using conventional package assembly method / tools is the most cost-effective way of making 3D-Packages. But fine pitch (100um) and low standoff interconnections between multiple-chips by single re-flow is challenging.…”

Section: Introductionmentioning

confidence: 99%

Three chips stacking with low volume solder using single re-flow process

Khan

Wee

Chiew

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch microjoints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step.

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Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps

Cited by 46 publications

References 9 publications

Using SOM neural network for X-ray inspection of missing-bump defects in three-dimensional integration

Using SOM neural network for X-ray inspection of missing-bump defects in three-dimensional integration

Structure effects on the electrical reliability of fine-pitch Cu micro-bumps for 3D integration

Three chips stacking with low volume solder using single re-flow process

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