Three-dimensional simulation of inverse narrow-channel effect

Sato, Naoyuki; Konaka, M.; Dang, Ryo

doi:10.1049/el:19820187

Cited by 35 publications

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“…The hamp appearing in subthreshold characteristics of MOSFETs fabricated on BOX type structures is known as the result of electric field enhancement at the edge of silicon mesa (3,4). It has been demonstrated by both simulation and experiments that the hamp can be suppressed by proper ion implantation to side walls, and that the required boron dose is reduced by tapering the side wall.…”

Section: Device Characteristicsmentioning

confidence: 99%

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

Shibata

Nakayama²,

Kurosawa³

et al. 1983

1983 International Electron Devices Meeting

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A simplified version of BOX isolation technology is described. The new process has been greatly simplified over the original BOX by introducing an additional non-critical masking step. The body effect o b s e r v e d i n n a r r o w c h a n n e l d e v i c e s i s r e d u c e d i n t h e n e w s t r u c t u r e . T h e c a p a c i t a n c e m e a s u r e m e n t o n d i f f u s e d junctions in BOX structure shows smaller c o n t r i b u t i o n s f r o m d i o d e p e r i m e t e r a s compared to LOCOS structure. Hot electron reliability of small geometry MOSFETs has been also studied and the results are presented and discussed.

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Section: Device Characteristicsmentioning

confidence: 99%

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

Shibata

Nakayama²,

Kurosawa³

et al. 1983

1983 International Electron Devices Meeting

Self Cite

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“…RSCE may lead to non-monotonic changes in drain current, as a function of channel length, under subthreshold operation, in both PMOS and NMOS transistors [8], [9]. Another secondary effect, the INWE, reduces the threshold voltage with decreasing channel width [11]. Minimum-sized devices have traditionally been said to be optimal to optimize speed, power-or energy consumption [3], [8].…”

Section: Introductionmentioning

confidence: 99%

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS

Vatanjou

Ytterdal

Aunet

2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

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This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder ("RCA"), demonstrating functionality for a supply voltage ("V dd ") down to 84 mV. The low V dd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect ("RSCE") to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low V dd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA. 6th Asia Symposium on Quality Electronic Design

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“…On the other hand, V T decreases with W g for CMOS technology with STI isolation. This is known as the Reverse Narrow Width Effect (RNWE) [57]. and non-recessed LOCOS isolation [58].…”

Section: Introductionmentioning

confidence: 99%

“…57 This graph monitors the AVGB shift from the DCIV current peaks when the transistor underwent maximum substrate hot-carrier stress condition.For short stress time, HCS PMOS I/O transistor (L ov = 0.31 urn) generated more hole trappings in the gate oxide as compared to that of a LCS PMOS I/O transistor (L ov of 5 urn). This figure can be used to explain the reason for the degradation of I DL IN over longer stress time as shown in Figure 7-52 and Figure 7-53.…”

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confidence: 99%

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

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Three-dimensional simulation of inverse narrow-channel effect

Cited by 35 publications

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A simplified box (buried-oxide) isolation technology for megabit dynamic memories

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS

Effects of small gate length, gate width and s/d overhang on mosfets isolated by STI technology

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