Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In<sub>0.53</sub>Ga<sub>0.47</sub>As GAA MOSFET

Copies of full items can be used for personal research or study, educational, or not-for profit purposes without prior permission or charge. Provided that the authors, title and full bibliographic details are credited, a hyperlink and/or URL is given for the original metadata page and the content is not changed in any way.Publisher's statement: "© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works." A note on versions:The version presented here may differ from the published version or, version of record, if you wish to cite this item you are advised to consult the publisher's version. Please see the 'permanent WRAP url' above for details on accessing the published version and note that access may require a subscription. Abstract-The fin edge roughness (FER) and the TiN metal grain work-function (MGW) induced variability affecting off and on device characteristics is studied and compared between a 10.4 nm gate length In 0.53 Ga 0.47 As FinFET and a 10.7 nm gate length Si FinFET. We have analysed the impact of variability by assessing five figures of merit (V T , SS, I OFF , DIBL and I ON ) using two state-of-the-art in-house-build 3-D simulation tools based on the finite element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the sub-threshold region while, in the on-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In 0.53 Ga 0.47 As FinFET is more resilient to the FER and MGW variability in the sub-threshold compared to the Si FinFET due to a stronger quantum carrier confinement present in the In 0.53 Ga 0.47 As channel. However, the on-current variability is between 1.1-2.2 times larger for the In 0.53 Ga 0.47 As FinFET than for the Si counterpart, respectively.

Section: Finfet Modellingmentioning

confidence: 99%

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Seoane

Indalecio

Aldegunde

et al. 2016

“…Existing RDF studies on III-V devices typically focus on inversion-mode device operation [8] and/or lack meaningful comparisons against equivalently designed and operated Si devices [9]. In particular, there is no clear understanding of whether III-V-based JLFETs are more or less vulnerable to RDF compared with equivalent Si-based designs.…”

Section: Introductionmentioning

confidence: 99%

Junctionless Silicon and In_0.53Ga_0.47As Transistors—Part II: Device Variability From Random Dopant Fluctuation

Leung

Pan

Chui

2015

Random dopant fluctuation (RDF) variability in nanoscale junctionless FETs (JLFETs) utilizing either Si orIn 0.53 Ga 0.47 As channels has been studied using technology computer-aided design (TCAD) simulations. The 15nm node Si and InGaAs JLFETs are equivalently designed and calibrated using nonequilibrium Green's function simulations for statistical TCAD analysis. We find that n-InGaAs JLFETs exhibit reduced RDF variability compared with n-Si JLFETs in terms of threshold voltage, subthreshold swing, and drain-induced barrier lowering as a result of high degeneracy effects. By contrast, the variability of p-InGaAs JLFETs is comparable with that of n-and p-Si JLFETs because of the larger valence band density of states (DOS). The normalized variations in ON-state drive current are roughly equal (∼16%) for all device types, because the major effects of degenerate screening on current transport effectively cancel one another. From these results, we find that high carrier degeneracy in small DOS materials can have a significant effect on the electrostatic integrity of JLFETs in the presence of RDF (especially in subthreshold), and that degenerately doped n-InGaAs devices are slightly (and inherently) more immune to RDF compared with Si JLFETs.

“…Finally, we have compared the Poisson Voronoi Diagram (PVD) variability against the Rayleigh model for both TiN and TaN metal gates. The PVD is an optimum method [17], [18] to generate metal grains since this approach represents the shape of domains that grow from randomly placed nucleation points as observed in a real fabrication [10], and the grain distribution generated matches the experimental results. We have shown that the Rayleigh approach overestimates the device variability (by 11.9% for the TiN and by 7.14% for the TaN), whereas the variability provided by the Gamma distribution is much closer to the realistic metal gate induced device variability.…”

Section: Discussionmentioning

confidence: 83%

Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions

Indalecio

García‐Loureiro

Seoane

et al. 2016

We have demonstrated, via validation to experimental data for TiN and Ru, that the grains which appear in the metal gate stacks of nanoscale CMOS devices can be characterized via a two-parameter Gamma distribution (p-values 0.17 and 0.42 for TiN and Ru). Conversely, a previously presented fit which used Rayleigh distribution does not reproduce the experimental data (p-values 3 × 10 −14 and 0.0029 for TiN and Ru). Poisson Voronoi Diagrams (PVDs) are shown as a suitable algorithm to generate grains with Gamma distribution, via fitting of the distribution of 10000 grains. We have also compared the PVD variability against the Rayleigh model. for both TiN and TaN metal gates, and concluded that Rayleigh approach overestimates the device variability (by 11.9% for the TiN and by 7.14% for the TaN).