Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node

Jung, Soon‐Moon; Jang, Jaehoon; Cho, Wonseok; Cho, Hoosung; Jeong, Jae−Hun; Chang, Young‐Jin; Kim, Jonghyuk; Rah, Youngseop; Son, Yangsoo; Park, Junbeom; Song, Minsung; Kim, Kyoung-Hon; Lim, Jin-soo; Kim, Kinam

doi:10.1109/iedm.2006.346902

Cited by 93 publications

(36 citation statements)

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“…In order to limit wafer cost, number of vertical layers must be as low as possible and, to compensate this limitation, it is fundamental to use small single cells. Many publications using this array organization have been presented [13,14]. Flexibility and reuse of know-how developed with planar CT cells are probably the reasons to explain the remarkable activity in this area.…”

Section: D Stacked Architecturementioning

confidence: 96%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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In planar Flash memories the most popular memory cell is based on the Floating Gate (FG) technology, whose cross section is shown in Fig. 3.1. Cross section and the associated floating gate model are sketched in Fig. 3.2. Basically, a MOS transistor is built with two overlapping gates: the first one (FG) is completely surrounded by oxide, while the second one forms the Control Gate (CG) terminal. The isolated gate constitutes an excellent "trap" for electrons, enabling long charge retention. The operations used to inject and remove electrons from the isolated gate are called Program and Erase, respectively. These operations modify the threshold voltage V TH of the memory cell, which is, at the end of the day, a MOS transistor. By applying a fixed voltage to the cell's terminals, it is then possible to discriminate two storage levels: when the gate voltage is higher than V TH , the cell is ON ("1"), vice versa it is OFF ("0").To minimize the space on silicon, memory cells are packed together to form a matrix. Depending on how the cells are organized inside the matrix, it is possible to distinguish between NAND and NOR Flash memories. NAND memories are the most widespread in the storage systems; NOR architecture is described in great details in [1].In the NAND string, memory cells are connected in series, in groups of 32, 64, 128, or even 150 [2], as shown in Fig. 3.3. Two select transistors are placed at the edges of the string, to ensure the connection to the source line (through M SL ) and to

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Section: D Stacked Architecturementioning

confidence: 96%

3D Stacked NAND Flash Memories

Micheloni

Crippa

2016

3D Flash Memories

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“…The 3D stackable NAND Flash devices (Jung et al 2006;Lai et al 2006) were demonstrated in 2006, where both single crystal silicon (Jung et al 2006) (by an epitaxial Si process) and poly-silicon TFT (Lai et al 2006) charge-trapping SONOS-type devices were demonstrated, as shown in Fig. 4.1.…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 99%

3D NAND Flash Architectures

Lue

2015

Charge-Trapping Non-Volatile Memories

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“…It forms transistors inside on-chip interconnect layer [3], on poly-silicon films [18], or on single-crystal silicon films [32], [33]. Although a drastically high vertical interconnect density can be realized, it is not readily compatible to existing fabrication processes and is subject to severe process temperature constraints that tend to dramatically degrade the circuit electrical performance.…”

Section: Transistor Build-up 3d Technologymentioning

confidence: 99%

DSP Systems using Three-Dimensional (3D) Integration Technology

Zhang¹,

Pan²,

Li³

2010

Handbook of Signal Processing Systems

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As three-dimensional (3D) integration technology is quickly maturing and steadily entering mainstream markets, it has begun to attract exploding interest from integrated circuit and system designers. This chapter discusses and demonstrates the exciting opportunities and potentials for digital signal processing (DSP) circuit and system designers to exploit 3D integration technology. In particular, this chapter advocates a 3D logic-DRAM integration paradigm and addresses the use of 3D logic-memory integration in both programmable digital signal processors and application-specific digital signal processing circuits. To further demonstrate the potential, this chapter presents case studies on applying 3D logic-DRAM integration to clustered VLIW (very long instruction word) digital signal processors and application-specific video encoders. Since DSP systems using 3D integration technology is still in its research infancy, by presenting some first discussions and results, the aim of this chapter is to motivate greater future efforts from DSP system research community to explore this new and rewarding research area.

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Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node

Cited by 93 publications

References 0 publications

3D Stacked NAND Flash Memories

3D Stacked NAND Flash Memories

3D NAND Flash Architectures

DSP Systems using Three-Dimensional (3D) Integration Technology

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