Three-Operand Floating-Point Adder

Yao, Tao; Gao, Deyuan; Fan, Xiaoya; Ren, Xiaomin

doi:10.1109/cit.2012.58

Cited by 19 publications

(11 citation statements)

References 3 publications

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“…The traditional fused floating-point three-term adder reduces the area, latency and power consumption compared to the discrete floating-point three-term adder by sharing the common logic [9], [10]. However, it is an initial design so that optimizations can be applied to improve the performance.…”

Section: An Improved Fused Floating-point Three-term Addermentioning

confidence: 97%

“…Fig. 2 shows a traditional fused floating-point three-term adder [9], [10]. The traditional floating-point three-term adder takes three operands and performs the two additions at once.…”

Section: Traditional Fused Floating-point Three-term Addersmentioning

confidence: 99%

“…Although the floating-point adders are well-optimized for two-term addition, the discrete design for the three-term adder takes twice the area, latency and power consumption of a single floating-point adder. In order to reduce the overhead, a fused floating-point three-term adders have been proposed, which performs two additions in a single unit [9], [10]. Fig.…”

Section: Traditional Fused Floating-point Three-term Addersmentioning

confidence: 99%

“…As a result adding a three-term adder does not require a special data path or register file. Several issues for the design of the fused floating-point three-term adder are discussed in the previous work [9], [10]: 1) Complex exponent processing and significand alignment, 2) Complementation after the significand addition, 3) Large precision significand addition, 4) Massive cancellation management, and 5) Complex round processing. In this paper, those issues are addressed by investigating several optimization techniques.…”

Section: Introductionmentioning

confidence: 99%

“…In order to reduce the overhead, fused floating-point units have been proposed, which execute several operations in a single unit to reduce the area, power consumption and latency. Several fused floating-point units have been introduced: Fused Multiply-Add (FMA) [2]- [4], fused add-subtract [5], [6], fused dot product [7], [8] and fused three-term adder [9], [10].…”

Section: Introductionmentioning

confidence: 99%

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A Fused Floating-Point Three-Term Adder

Sohn

Swartzlander

2014

IEEE Trans. Circuits Syst. I

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This paper presents improved architectures for a fused floating-point three-term adder. The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for both single and double precision and synthesized with a 45 nm CMOS standard-cell library. The improved fused floating-point three-term adder reduces the area and power consumption by about 20% and reduces the latency by about 35% compared to a discrete floating-point three-term adder. Based on the data flow analysis, the proposed three-term adder can be split into three pipeline stages. Since the latencies of three pipeline stages are fairly well balanced, the throughput is increased to 2.7 times that of the non-pipelined design.Index Terms-Floating-point arithmetic, fused floating-point operations, high speed computer arithmetic, three-term adder.

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Section: An Improved Fused Floating-point Three-term Addermentioning

confidence: 97%

“…Fig. 2 shows a traditional fused floating-point three-term adder [9], [10]. The traditional floating-point three-term adder takes three operands and performs the two additions at once.…”

Section: Traditional Fused Floating-point Three-term Addersmentioning

confidence: 99%