Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

Iyengar, Anirudh; Vontela, Deepak; Reddy, Ithihasa; Ghosh, Swaroop; Motaman, Syedhamidreza; Jang, Jae-Won

doi:10.1145/3218603.3218641

Cited by 10 publications

(4 citation statements)

References 15 publications

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“…In such a case, the carrier mobility reduction is significantly contrasted by the lower threshold voltage, which, in turn, lead to a propagation delay reduction. This behavior is expected to be much more evident when ROs are realized on FPGA platforms exploiting a massive usage of PT logic circuits [34], [35]. By transistor-level simulations performed by using a standard CMOS process technology, we investigated the effects of the coexistence of PT and static CMOS logic stages, typically occurring in the target platform.…”

Section: Temperature Sensitivitymentioning

confidence: 99%

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization

Spagnolo,

Perri,

Vatalaro

et al. 2024

IEEE Trans. VLSI Syst.

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Ring oscillators (ROs) serve as basic building blocks in a lot of application scenarios, where they must ensure high reliability, flexibility, and low-area/energy footprint. With the recent advances of the Internet-of-Things (IoT) technology, in particular, the necessity to endow interconnected devices with security facilities has increased as well. In this context, the efficient implementation of ROs on field-programmable gate arrays (FPGAs) is crucial, even though it hides some pitfalls. This article presents a new design strategy for multistage ROs relying on the carry chains (CCs) available into modern FPGA devices. Several configurations of ROs designed as proposed here have been characterized in terms of hardware costs, jitter, and temperature/voltage sensitivity. In all the evaluated cases, the proposed design allows to achieve predictable routing schemes through the automatic place and route (P&R), while reducing slice occupancy and energy consumption by up to 50% and 44%, respectively, in comparison with the traditional lookup table (LUT)-based ROs. When realized on a Artix-7 device, the basic version of the proposed oscillator realized using 33 inverting stages allows obtaining multiphase outputs oscillating at 29.7 MHz with a standard deviation less than 10 kHz. The analysis conducted also demonstrates the high flexibility of the novel circuits, such as the possibility to easily change their behavior depending on the target application requirements. As an example, by exploiting additional pass-through elements, the proposed scheme achieves a sensitivity of 49 kHz/ • C that is more than 4 times higher than that shown by the corresponding traditional LUT-based competitor, thus making it more suitable for thermal monitoring applications.

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Section: Temperature Sensitivitymentioning

confidence: 99%

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization

Spagnolo,

Perri,

Vatalaro

et al. 2024

IEEE Trans. VLSI Syst.

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“…Collantes et al [54] adopted domino logic to implement their TVCs. Recently, Iyengar et al [64] demonstrated two flavors of TVC in STMicroelectronics 65nm technology. In principle, TVC schemes offer better resilience than other LC schemes as regular etching and optical-imaging techniques are ineffective.…”

Section: Advanced Layout Camouflaging Schemesmentioning

confidence: 99%

Protect Your Chip Design Intellectual Property

Knechtel

Patnaik

Sinanoglu

2019

Proceedings of the International Conference on Omni-Layer Intelligent Systems

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The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work. CCS CONCEPTS• Security and privacy → Security in hardware;

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“…Thus, there is motivation for developing countermeasures to SEM-based RE. To disrupt the attacker's ability to identify logic gates from SEM images, camouflaging techniques such as manipulating the threshold voltage [12], [13], [14] of transistors and dummy contacts [11] have been proposed. However, in these early camouflaging processes, the attacker knows which cells are camouflaged in the design.…”

Section: Introductionmentioning

confidence: 99%

Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates

Farheen

Botero

Varshney

et al. 2021

International Symposium for Testing and Failure Analysis

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IC camouflaging has been proposed as a promising countermeasure against malicious reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as one single layout under microscope imaging, thereby hiding the real circuit functionality from adversaries. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits and thus being resilient against various invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis was only performed on simplified dummy contact structures in prior work. Whether the e-beam during SEM imaging will charge differently on different contacts and further reveal the different structures or not requires extended research. In this study, we fabricated real and dummy contacts in various structures and performed a systematic SEM imaging analysis to investigate the possible charging and the consequent passive voltage contrast on contacts. In addition, machine-learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant in SEM imaging, which effectively prevents adversarial SEM-based reverse engineering. Index Terms—Reverse Engineering, IC Camouflaging, Scanning Electron Microscopy, Machine Learning, Countermeasure.

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Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

Cited by 10 publications

References 15 publications

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization

Protect Your Chip Design Intellectual Property

Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates

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