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Non-volatile memories are gaining significant attention for embedded cache application due to low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we provide a physics-based model of domain wall that comprehends process variations (PV) and Joule heating. The proposed model has been used for circuit simulation. We also propose techniques to mitigate the impact of variability and Joule heating while enabling low-power and high frequency operation.

Physically Unclonable Function (PUF) is a security primitive to address hardware security issues such as chip authentication, Intellectual Property (IP) protection etc. Conventional CMOS PUFs are built on delay (inverter chains, scan chains etc.) or memory structures (like SRAM). In this paper, we propose a novel PUF which works on the principles of spintronic Domain Wall Memory (DWM). Conventional DWM is limited by pinning due to process variations induced surface roughness of the nanowire. We exploit this limitation towards chip-authentication. We propose two flavors of PUFs namely relay-PUF and memory-PUF. The proposed PUFs show excellent entropy (measured by Hamming Distance). We also analyze metrics such as robustness, area and power of the DWM-PUFs. The memory-PUF indicated up to an order of magnitude reduction in power compared to SRAM PUF.

We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop. Index Terms-Enhanced scan (ES), magnetic tunnel junction (MTJ), nonvolatile flip-flop (NVFF), power gating.

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