Spin-Transfer Torque Random Access Memory (STTRAM) is a possible candidate for universal memory due to its high-speed, low-power, non-volatility, and low cost. Although attractive, STTRAM is susceptible to contactless tampering through malicious exposure to magnetic field with the intention to steal or modify the bitcell content. In this paper, for the first time to our knowledge, we analyze the impact of magnetic attacks on STTRAM using micro-magnetic simulations. Next, we propose a novel array-based sensor to detect the polarity and magnitude of such attacks and then propose two design techniques to mitigate the attack, namely, array sleep with encoding and variable strength Error Correction Code (ECC). Simulation results indicate that the proposed sensor can reliably detect an attack and provide sufficient compensation window (few ns to ~100us) to enable proactive protection measures. Finally, we shows that variable-strength ECC can adapt correction capability to tolerate failures with various strength of an attack.

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Non-volatile memories (NVMs) such as Spin-Transfer Torque RAM (STTRAM) have drawn significant attention due to complete elimination of bitcell leakage. In addition to the plethora of benefits such as density, non-volatility, low-power and high speed, majority of Non-Volatile Memories (NVMs) are also compatible with CMOS technology enabling easy integration. Although promising, NVM brings new security challenges that were absent in their conventional volatile memory counterparts such as Static RAM (SRAM) and embedded Dynamic RAM (eDRAM). The root cause is persistent data that may allow the adversary to retrieve sensitive information like password or cryptographic keys. This is primarily due to the fundamental dependency of these memory technologies on environmental parameters such as magnetic fields and temperature which can be exploited by the adversary to tamper with the stored data. This paper investigates the data security and privacy challenges in NVMs by exploring the security specific properties and novel security primitives realized using spintronic building blocks. A thorough analysis is done on the vulnerabilities, data security and privacy issues, threats and possible countermeasures to enable safe computing environment using spintronics.

Physical Unclonable Function (PUF) is a cost-effective security primitive to address hardware attacks such as cloning, impersonation and Intellectual Property (IP) violation. Static Random-Access Memory (SRAM) PUF has been proposed; however, it suffers from challenges, some of which are environmental fluctuations such as voltage, temperature, and noise. Ensuring the robustness of SRAM PUF under such conditions is challenging. In this paper, we propose 8T SRAM PUF with a back-to-back PMOS latch to improve robustness by 4X. We also propose a low-power 7T SRAM with embedded Magnetic Tunnel Junction (MTJ) devices to enhance the robustness (2.3X to 20X) while lowering the leakage power and area overhead.

We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop. Index Terms-Enhanced scan (ES), magnetic tunnel junction (MTJ), nonvolatile flip-flop (NVFF), power gating.