Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory

Iyengar, Anirudh; Ghosh, Swaroop

doi:10.1145/2593069.2593161

Cited by 30 publications

(15 citation statements)

References 19 publications

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“…The LLG is solved with the pinning sites in order to observe the impact of DW dynamics. In practice, several techniques have been suggested to mitigate the effect of variations [20]. However, we demonstrate that it can be exploited to generate challenge-response pairs for authentication.…”

Section: B Process Variation Modeling and Analysismentioning

confidence: 97%

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DWM-PUF: A low-overhead, memory-based security primitive

Iyengar

Ramclam

Ghosh

2014

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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Physically Unclonable Function (PUF) is a security primitive to address hardware security issues such as chip authentication, Intellectual Property (IP) protection etc. Conventional CMOS PUFs are built on delay (inverter chains, scan chains etc.) or memory structures (like SRAM). In this paper, we propose a novel PUF which works on the principles of spintronic Domain Wall Memory (DWM). Conventional DWM is limited by pinning due to process variations induced surface roughness of the nanowire. We exploit this limitation towards chip-authentication. We propose two flavors of PUFs namely relay-PUF and memory-PUF. The proposed PUFs show excellent entropy (measured by Hamming Distance). We also analyze metrics such as robustness, area and power of the DWM-PUFs. The memory-PUF indicated up to an order of magnitude reduction in power compared to SRAM PUF.

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Section: B Process Variation Modeling and Analysismentioning

confidence: 97%

“…In order to study the impact of variations we first model the relationship between depinning magnetic field (Hth) and its dependency on notch depth (nt) for the NW [17,18,20]. Next we study the presence of single notch at qpin=0 under process variation induced notch width (d) and depth (nt) fluctuations.…”

Section: B Process Variation Modeling and Analysismentioning

confidence: 99%

DWM-PUF: A low-overhead, memory-based security primitive

Iyengar

Ramclam

Ghosh

2014

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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“…It reduces 92% leakage power compared with DRAM [2,3]. DWM shows great potential in replacing current memory technologies in various application areas [4,5], such as imPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.…”

Section: Introductionmentioning

confidence: 99%

Optimizing data placement for reducing shift operations on domain wall memories

Chen

Sha

Zhuge

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Domain Wall Memory (DWM) using nanowire with data access port, exhibits extraordinary high density, low power leakage, and low access latency. These properties enable DWM to become an attractive candidate for replacing traditional memories. However, data accesses on DWM may require multiple shift operations before the port points to requested data, resulting in varying access latencies. Data placement, therefore, has a significant impact on the performance of data accesses on DWM. This paper studies compiler-based optimization techniques for data placement on DWM. To the authors' best knowledge, this is the first work addressing data placement problem on DWM. We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. The experimental results show that GBDP has a significant performance improvement; for example, GBDP reduces 82% shift operations on an 8-port DWM compared with non-optimized approach.

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“…Non-volatile memory devices (such as memristor) together with CMOS transistors offer several opportunities in the next generation high performance systems [1] [2] [3]. Memristor stores information bits as the resistance value imposed on a resistive-variable device.…”

Section: Introductionmentioning

confidence: 99%

2T2M memristor based TCAM cell for low power applications

Yang¹,

Mathew²,

Ottavi

et al. 2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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This paper presents a 2-transistors-memristors (2T2M) bitcell for content-addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach

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Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory

Cited by 30 publications

References 19 publications

DWM-PUF: A low-overhead, memory-based security primitive

DWM-PUF: A low-overhead, memory-based security primitive

Optimizing data placement for reducing shift operations on domain wall memories

2T2M memristor based TCAM cell for low power applications

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