Threshold logic synthesis based on cut pruning

Neutzling, Augusto; Matos, Jody Maick; Reis, André I.; Ribas, Renato P.; Mishchenko, Alan

doi:10.1109/iccad.2015.7372610

Cited by 13 publications

(3 citation statements)

References 16 publications

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“…Another possible disadvantage of this approach is that it may use arithmetic operators of maximum width, regardless of how small the results of the partial sums are. 2 There are two basic approaches to decompose a given threshold function into a network of bounded fanin threshold functions, several heuristic approaches [25], [26] view the threshold function as any other logic function, and use existing logic synthesis tools to perform a technology-independent resynthesis into a traditional logic network. This logic network is searched for subgraphs that are bounded-fanin threshold functions.…”

Section: Binary Neural Network Using Binary Neuronsmentioning

confidence: 99%

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

Wagle

Khatri

Vrudhula

2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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This paper presents TULIP, a new architecture for a binary neural network (BNN) that uses an optimal schedule for executing the operations of an arbitrary BNN. It was constructed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a SIMD fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. The unique aspect of the binary neuron is that it is implemented as a mixed-signal circuit that natively performs the inner-product and thresholding operation of an artificial binary neuron. Moreover, the binary neuron, which is implemented as a single CMOS standard cell, is reconfigurable, and with a change in a single parameter, can implement all standard operations involved in a BNN. We present novel algorithms for mapping arbitrary nodes of a BNN onto the TULIP-PEs. TULIP was implemented as an ASIC in TSMC 40nm-LP technology. To provide a fair comparison, a recently reported BNN that employs a conventional MAC-based arithmetic processor was also implemented in the same technology. The results show that TULIP is consistently 3X more energy-efficient than the conventional design, without any penalty in performance, area, or accuracy.

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Section: Binary Neural Network Using Binary Neuronsmentioning

confidence: 99%

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

Wagle

Khatri

Vrudhula

2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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“…A flash device is programmed by holding its body, source and drain nodes at the ground and applying a high voltage (10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20) to the control gate. The resulting electric field forces electrons to tunnel from the substrate into the floating gate, increasing the threshold voltage of the flash transistor.…”

Section: B Flash Transistorsmentioning

confidence: 99%

Threshold Logic in a Flash

Wagle¹,

Singh²,

Yang³

et al. 2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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This paper describes a novel design of a threshold logic gate (a binary perceptron) and its implementation as a standard cell. This new cell structure, referred to as flash threshold logic (FTL), uses floating gate (flash) transistors to realize the weights associated with a threshold function. The threshold voltages of the flash transistors serve as a proxy for the weights. An FTL cell can be equivalently viewed as a multi-input, edge-triggered flipflop which computes a threshold function on a clock edge. Consequently, it can be used in the automatic synthesis of ASICs. The use of flash transistors in the FTL cell allows programming of the weights after fabrication, thereby preventing discovery of its function by a foundry or by reverse engineering. This paper focuses on the design and characteristics of the FTL cell. We present a novel method for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm. The algorithm is further extended to select weights to maximize the robustness of the design in the presence of process variations. The FTL circuit was designed in 40nm technology and simulations with layout-extracted parasitics included, demonstrate significant improvements in the area (79.7%), power (61.1%), and performance (42.5%) when compared to the equivalent implementations of the same function in conventional static CMOS design. Weight selection targeting robustness is demonstrated using Monte Carlo simulations. The paper also shows how FTL cells can be used for fixing timing errors after fabrication.

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“…Fig. 2 Different threshold logic synthesis flows: (a) previous works from other authors, (b) proposed in[42]; (c) proposed in[19].…”

mentioning

confidence: 99%

Logic Synthesis for Emerging Technologies

Neutzling¹,

Ribas²

2021

JICS

Self Cite

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Emerging technologies are being considered to replace the conventional CMOS-based design that seems arriving to its end of life due to the limits of MOS transistor shrinking. However, since those novel devices are not necessarily switch-based ones, the traditional AND/OR logic synthesis process in the digital integrated circuit design flow tends to become inefficient, whereas threshold logic paradigm seems to be more appropriate for them. In this context, different methods for threshold logic synthesis, suitable for emerging technologies, are reviewed in this paper. The majority logic based design is also discussed herein since it represents a subset of threshold logic domain, and many new technologies have presented the 3-input majority Boolean function as the most basic logic gate. Experimental data, presented in previous works, are used to illustrate and compare the performance of the state-ofthe-art logic synthesis methods related to

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Threshold logic synthesis based on cut pruning

Cited by 13 publications

References 16 publications

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells

Threshold Logic in a Flash

Logic Synthesis for Emerging Technologies

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