Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling

Cai, Yu; Haratsch, Erich F.; Mutlu, Onur; Mai, Ken

doi:10.7873/date.2013.266

Cited by 230 publications

(243 citation statements)

References 8 publications

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“…We test 2-bit MLC NAND flash memory devices manufactured in 2Y-nm technology. We use the read-retry feature present in these devices to accurately read threshold voltages of cells, as described in [8]. Our previous work describes our characterization platform in detail [8] [9].…”

Section: Experimental Testing Platform and Methodologymentioning

confidence: 99%

“…Evaluation Results: Using an FPGA platform [8][9], we tested the raw bit error rate (BER) with and without read reference voltage prediction. Results are shown in Fig.…”

Section: Basic Ideamentioning

confidence: 99%

“…In MLC NAND flash memory, the logical value stored in a memory cell is determined by the threshold voltage range into which the cell's actual threshold voltage falls [8]. Program interference is the phenomenon in which the threshold voltage of a flash cell, called the victim cell, unintentionally changes (i.e., gets disturbed) while another cell's value is being programmed [3][4] [15] [16].…”

Section: Introductionmentioning

confidence: 99%

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Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors.In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.

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Section: Experimental Testing Platform and Methodologymentioning

confidence: 99%

“…Evaluation Results: Using an FPGA platform [8][9], we tested the raw bit error rate (BER) with and without read reference voltage prediction. Results are shown in Fig.…”

Section: Basic Ideamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Cai

Mutlu

Haratsch³

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

Self Cite

169

200

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“…1. The threshold voltage distribution is affected by the program/erase (P/E) cycling endurance [8], and our task is to estimate the parameters of this distribution by the EM algorithm and then update the LLR values for LDPC soft decoding. We first conduct multiple reads operation with Q distinct read voltages, labeled as V 1 to V Q .…”

Section: Em Algorithm For Mlc Nand Flash Memorymentioning

confidence: 99%

“…In order to apply the EM algorithm to MLC NAND Flash memory, read retry feature [8] should be supported by NAND flash memory chips. Consider the threshold voltage distribution of MLC NAND flash memory shown in Fig.…”

Section: Em Algorithm For Mlc Nand Flash Memorymentioning

confidence: 99%

Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory

Peng

Wang

et al. 2017

IEICE Electron. Express

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A dynamic log-likelihood ratio (DLLR) scheme based on expectation-maximization (EM) algorithm for the decoding of low-density parity-check (LDPC) codes in NAND flash memory is proposed. When LDPC soft decoding fails, the DLLR scheme employs the EM algorithm to estimate the parameters of the threshold voltage distribution of NAND flash memory, and then recalculates the LLR values for decoding. Simulation results show that the proposed scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.

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Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling

Cited by 230 publications

References 8 publications

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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