Threshold voltage model for deep-submicrometer MOSFETs

liu, zhenglin; Hu, Chenming; Huang, Jian; Chan, T.Y.; Jeng, Min-Chie; Ko, P.K.; Cheng, Yuhua

doi:10.1109/16.249429

Cited by 425 publications

(142 citation statements)

References 14 publications

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“…So we select some parameters of MOS transistor and circuits as machine learning`s features, and path delay as machine learning`s target. According to [8], [9], [10], [11], we set some parameters of MOS in Table 2: Table 2. Some parameters of MOS transistor.…”

Section: Methods Of Circuit Parametersmentioning

confidence: 99%

Standard Cell Library Characterization of 28nm Process Based on Machine Learning

She¹,

Zhang²,

Zheng³

et al. 2017

dtcse

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Abstract. This article presents a new learning method based on machine learning, which can quickly and accurately draw up the characterization of the Static Random-Access Memory (SRAM) compiler and standard cell library. The timing of 10 standard circuits with different process corners and their key parameters were collected. According to the 10-fold cross validation, the regression model was established by linear regression. After comparing the influence of different parameters on path delay, determination coefficient of training set and testing set were 0.979 and 0.955, respectively. Relative Error of training set and test set were 0.9458 and 0.8736, respectively. Then, the timing of a D type flip-flop (DFF) was selected as the target of the regression. At the same time, the determination coefficients of the regression model training set and the testing set are 0.9992 and 0.9992, respectively. Relative Error of training set and test set were 0.9882 and 0.9868, respectively. The results show that the model fitted the timing of DFF by the path delay of other circuits is better than the previous method.

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Section: Methods Of Circuit Parametersmentioning

confidence: 99%

Standard Cell Library Characterization of 28nm Process Based on Machine Learning

She¹,

Zhang²,

Zheng³

et al. 2017

dtcse

View full text Add to dashboard Cite

show abstract

“…Increasing the number of dislocations by a factor of 10, for instance by increasing the channel width from 1 µm to 10 µm, results in a decrease of V T from about´400 mV tó 150 mV for nMOSFETs. An explanation could be the dependence of V T and the subthreshold voltage shift (∆V T ) on the effective channel length of MOSFETs [60]. Decreasing the effective channel length results in an increase of ∆V T .…”

Section: Electrical Measurements On Dislocationsmentioning

confidence: 99%

Electronic and Optical Properties of Dislocations in Silicon

Reiche

Kittler

2016

Crystals

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Dislocations exhibit a number of exceptional electronic properties resulting in a significant increase of the drain current of metal-oxide-semiconductor field-effect transistors (MOSFETs) if defined numbers of these defects are placed in the channel. Measurements on individual dislocations in Si refer to a supermetallic conductivity. A model of the electronic structure of dislocations is proposed based on experimental measurements and tight binding simulations. It is shown that the high strain level on the dislocation core-exceeding 10% or more-causes locally dramatic changes of the band structure and results in the formation of a quantum well along the dislocation line. This explains experimental findings (two-dimensional electron gas and single-electron transitions). The energy quantization within the quantum well is most important for supermetallic conductivity.

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“…The latter is defined as the variation of the threshold voltage with respect to the applied drain-to-source voltage, i.e. ∂V T /∂V DS and can be modeled as [17]- [19] …”

Section: B the Small-signal DC Modelmentioning

confidence: 99%

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

Enz

Chicco

Pezzotta

2017

IEEE Solid-State Circuits Mag.

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Abstract-This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient IC is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT 0 and spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40-nm and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation valid from weak to strong inversion and requiring only the VS parameter λc is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuit, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to strong inversion with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G ds /ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for DIBL. The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted SOI (FDSOI) and FinFET 28-nm processes.

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Threshold voltage model for deep-submicrometer MOSFETs

Cited by 425 publications

References 14 publications

Standard Cell Library Characterization of 28nm Process Based on Machine Learning

Standard Cell Library Characterization of 28nm Process Based on Machine Learning

Electronic and Optical Properties of Dislocations in Silicon

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

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